Datasheet ARG81800 (Allegro) - 7

40 V, 500 mA / 1.0 A Synchronous Buck Regulators ARG81800 with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit LOW-POWER (LP) MODE
LP Output Voltage Ripple [3][4] ΔVOUT(LP) LP Mode, 8 V < VIN < 12 V − 65 − mV I Low I PEAK(LP1) ARG81800, No Load, VIN = 12 V 320 400 500 mA Q Peak Current Threshold IPEAK(LP2) ARG81800-1, No Load, VIN = 12 V 160 212 270 mA
INTERNAL POWER SWITCHES
T High-Side MOSFET On-Resistance R J =25°C [3], VBOOT – VSW = 4.5 V, IDS = 800 mA − 500 600 mΩ DS(on)HS TJ = 150°C, VBOOT – VSW = 4.5 V, IDS = 800 mA − − 1075 mΩ T Low-Side MOSFET On-Resistance R J =25°C [3], VIN ≥ 4.5 V, IDS = 1 A − 210 250 mΩ DS(on)LS TJ =150°C, VIN ≥ 4.5 V, IDS = 1 A − − 450 mΩ High-Side Leakage Current [5] ILKG(HS) TJ = 25°C, VIN = 12 V, VEN = 0 V, VSW = 0 V −1.5 − 1.5 µA Low-Side Leakage Current ILKG(HS) TJ = 25°C, VIN = 12 V, VEN = 0 V, VSW = 12 V −1.5 − 1.5 µA Gate Drive Non-Overlap Time [3] tNO − 10 25 ns Switch Node Rising Slew Rate SRHS 12 V < VIN < 16 V [3] − 5 − V/ns
MOSFET CURRENT PROTECTION THRESHOLDS
I High-Side Current Limit LIMHS1 tON = tON(MIN), ARG81800 1.7 2.0 2.3 A ILIMHS2 tON = tON(MIN), ARG81800-1 0.85 1.0 1.15 A Low-Side Current Limit ILIMLSx − 50 − % of ILIMHSx
SYNCHRONIZATION INPUT (SYNCIN PIN)
Synchronization Frequency Range fSW(SYNC) 0.25 − 2.5 MHz SYNCIN Duty Cycle DCSYNC 20 50 70 % SYNCIN Pulse Width tPWSYNC 80 − − ns V SYNC SYNC(HI) VSYNC(IN) rising − 1.35 1.5 V IN Voltage Thresholds VSYNC(LO) VSYNC(IN) falling 0.8 1.2 − V SYNCIN Hysteresis VSYNC(HYS) VSYNC(HI) ‒ VSYNC(LO) − 150 − mV SYNCIN Pin Current ISYNC VSYNC(IN) = 5 V − ±1 − µA
CLOCK OUTPUT (CLKOUT PIN)
SYNC RFSET = 14.3 kΩ, VSYNC(HI) = 3.3 V, IN to CLKOUT Delay ФSYNC(CLK) Dither disabled − 1/(2×fSW) ± 70 − ns SWMASTER to SWFOLLOWER Delay [3] ФSWM(SWF) RFSET = 14.3 kΩ, VSYNC(HI) = 3.3 V − 1/(2×fSW) ± 30 − ns V CLK CLK(OUT)H VVREG = 4.8 V 2.2 − − V OUT Output Voltages VCLK(OUT)L VVREG = 4.8 V − − 0.6 V Continued on next page... 7 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Typical Performance Characteristics Functional Description Overview Reference Voltage Internal VREG Regulator Oscillator/Switching Frequency Synchronization (SYNCIN) and Clock Output (CLOCKOUT) Frequency Dither Transconductance Error Amplifier Compensation Components Power MOSFETs BOOT Regulator Soft Start (Startup) and Inrush Current Control Slope Compensation Pre-Biased Startup Dropout PGOOD Output Current Sense Amplifier Pulse-Width Modulation (PWM) Low-Power (LP) Mode Protection Features Undervoltage Lockout (UVLO) Pulse-by-Pulse Peak Current Protection (PCP) Overcurrent Protection (OCP) and Hiccup Mode BOOT Capacitor Protection Asynchronous Diode Protection Overvoltage Protection (OVP) SW Pin Protection Pin-to-Ground and Pin-to-Short Protections Thermal Shutdown (TSD) Application Information Design and Component Selection PWM Switching Frequency (RFSET) Output Voltage Setting Output Inductor (LO) Output Capacitors (CO) Output Voltage Ripple – Ultralow-IQ LP Mode Input Capacitors Bootstrap Capacitor Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ, CZ, and CP) Power Stage Error Amplifier A Generalized Tuning Procedure Power Dissipation and Thermal Calculations EMI/EMC Aware PCB Design Typical Reference Designs Package Outline Drawing