Datasheet ARG81800 (Allegro) - 10
| Manufacturer | Allegro |
| Description | 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD |
| Pages / Page | 42 / 10 — 40 V, 500 mA / 1.0 A Synchronous Buck Regulators. ARG81800. with Ultralow … |
| File Format / Size | PDF / 4.0 Mb |
| Document Language | English |
40 V, 500 mA / 1.0 A Synchronous Buck Regulators. ARG81800. with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
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40 V, 500 mA / 1.0 A Synchronous Buck Regulators ARG81800 with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit BOOT REGULATOR (BOOT PIN)
BOOT Charging Frequency fBOOT − fSW − − BOOT Voltage VBOOT VIN = 12 V, VBOOT – VSW − 4.8 5.3 V
INTERNAL REGULATOR (VREG PIN)
BIAS Disconnected VVREG1 6 V < VVIN < 36 V, VBIAS = 0 V 4.5 4.8 5.1 V VBIAS = 3.3V 2.85 3.2 3.29 V BIAS Connected VVREG2 6 V < VBIAS < 20 V 4.5 4.8 5.1 V BIAS Input Voltage Range VBIAS 3.3 − 36 V
THERMAL SHUTDOWN PROTECTION (TSD)
TSD Rising Threshold [3] T TJ rising, PWM stops immediately and COMP TSD and SS are pulled low 155 170 − °C TSD Hysteresis [3] TSDHYS TJ falling, relative to TTSD − 20 − °C [1] Negative current is defined as coming out of the node or pin, positive current is defined as going into the node or pin. [2] Thermally limited depending on input voltage, duty cycle, regulator load currents, PCB layout, and airflow. [3] Ensured by design and characterization, not production tested. [4] Using recommended external components specified in Table 3. [5] At VIN = 36 V, IOUT = 0 A, and TJ = 150°C, VOUT rises to overvoltage threshold due to leakage. 10 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Typical Performance Characteristics Functional Description Overview Reference Voltage Internal VREG Regulator Oscillator/Switching Frequency Synchronization (SYNCIN) and Clock Output (CLOCKOUT) Frequency Dither Transconductance Error Amplifier Compensation Components Power MOSFETs BOOT Regulator Soft Start (Startup) and Inrush Current Control Slope Compensation Pre-Biased Startup Dropout PGOOD Output Current Sense Amplifier Pulse-Width Modulation (PWM) Low-Power (LP) Mode Protection Features Undervoltage Lockout (UVLO) Pulse-by-Pulse Peak Current Protection (PCP) Overcurrent Protection (OCP) and Hiccup Mode BOOT Capacitor Protection Asynchronous Diode Protection Overvoltage Protection (OVP) SW Pin Protection Pin-to-Ground and Pin-to-Short Protections Thermal Shutdown (TSD) Application Information Design and Component Selection PWM Switching Frequency (RFSET) Output Voltage Setting Output Inductor (LO) Output Capacitors (CO) Output Voltage Ripple – Ultralow-IQ LP Mode Input Capacitors Bootstrap Capacitor Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ, CZ, and CP) Power Stage Error Amplifier A Generalized Tuning Procedure Power Dissipation and Thermal Calculations EMI/EMC Aware PCB Design Typical Reference Designs Package Outline Drawing
40 V, 500 mA / 1.0 A Synchronous Buck Regulators ARG81800 with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit BOOT REGULATOR (BOOT PIN)
BOOT Charging Frequency fBOOT − fSW − − BOOT Voltage VBOOT VIN = 12 V, VBOOT – VSW − 4.8 5.3 V
INTERNAL REGULATOR (VREG PIN)
BIAS Disconnected VVREG1 6 V < VVIN < 36 V, VBIAS = 0 V 4.5 4.8 5.1 V VBIAS = 3.3V 2.85 3.2 3.29 V BIAS Connected VVREG2 6 V < VBIAS < 20 V 4.5 4.8 5.1 V BIAS Input Voltage Range VBIAS 3.3 − 36 V
THERMAL SHUTDOWN PROTECTION (TSD)
TSD Rising Threshold [3] T TJ rising, PWM stops immediately and COMP TSD and SS are pulled low 155 170 − °C TSD Hysteresis [3] TSDHYS TJ falling, relative to TTSD − 20 − °C [1] Negative current is defined as coming out of the node or pin, positive current is defined as going into the node or pin. [2] Thermally limited depending on input voltage, duty cycle, regulator load currents, PCB layout, and airflow. [3] Ensured by design and characterization, not production tested. [4] Using recommended external components specified in Table 3. [5] At VIN = 36 V, IOUT = 0 A, and TJ = 150°C, VOUT rises to overvoltage threshold due to leakage. 10 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Typical Performance Characteristics Functional Description Overview Reference Voltage Internal VREG Regulator Oscillator/Switching Frequency Synchronization (SYNCIN) and Clock Output (CLOCKOUT) Frequency Dither Transconductance Error Amplifier Compensation Components Power MOSFETs BOOT Regulator Soft Start (Startup) and Inrush Current Control Slope Compensation Pre-Biased Startup Dropout PGOOD Output Current Sense Amplifier Pulse-Width Modulation (PWM) Low-Power (LP) Mode Protection Features Undervoltage Lockout (UVLO) Pulse-by-Pulse Peak Current Protection (PCP) Overcurrent Protection (OCP) and Hiccup Mode BOOT Capacitor Protection Asynchronous Diode Protection Overvoltage Protection (OVP) SW Pin Protection Pin-to-Ground and Pin-to-Short Protections Thermal Shutdown (TSD) Application Information Design and Component Selection PWM Switching Frequency (RFSET) Output Voltage Setting Output Inductor (LO) Output Capacitors (CO) Output Voltage Ripple – Ultralow-IQ LP Mode Input Capacitors Bootstrap Capacitor Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ, CZ, and CP) Power Stage Error Amplifier A Generalized Tuning Procedure Power Dissipation and Thermal Calculations EMI/EMC Aware PCB Design Typical Reference Designs Package Outline Drawing
