Datasheet MTD1N60E (Motorola) - 7
| Manufacturer | Motorola |
| Description | TMOS E−FET Power Field Effect Transistor DPAK for Surface Mount. N−Channel Enhancement−Mode Silicon Gate |
| Pages / Page | 10 / 7 — INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE. RECOMMENDED … |
| Revision | XXX |
| File Format / Size | PDF / 239 Kb |
| Document Language | English |
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE. RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS
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MTD1N60E
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total between the board and the package. With the correct pad design. The footprint for the semiconductor packages must be geometry, the packages will self align when subjected to a the correct size to ensure proper solder connection interface solder reflow process. 0.165 0.118 4.191 3.0 0.100 2.54 0.063 1.6 0.190 0.243 4.826 6.172 inches mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a dissipation can be increased. Although one can almost double function of the drain pad size. These can vary from the the power dissipation with this method, one will be giving up minimum pad size for soldering to a pad size given for area on the printed circuit board which can defeat the purpose maximum power dissipation. Power dissipation for a surface of using surface mount technology. For example, a graph of mount device is determined by TJ(max), the maximum rated RθJA versus drain pad area is shown in Figure 15. junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating 100 temperature, T Board Material = 0.0625″ A. Using the values provided on the data sheet, G−10/FR−4, 2 oz Copper PD can be calculated as follows: 1.75 Watts 80 T TA = 25°C P J(max) − TA D = C/W) ANCE, JUNCTION ° Rθ ( JA 60 The values for the equation are found in the maximum RESIST 3.0 Watts AMBIENT ratings table on the data sheet. Substituting these values into TO the equation for an ambient temperature T 40 A of 25°C, one can 5.0 Watts calculate the power dissipation of the device. For a DPAK , THERMAL device, P JAθ D is calculated as follows. R 200 2 4 6 8 10 150°C − 25°C PD = = 1.75 Watts A, AREA (SQUARE INCHES) 71.4°C/W
Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)
The 71.4°C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit Another alternative would be to use a ceramic substrate or board to achieve a power dissipation of 1.75 Watts. There are an aluminum core board such as Thermal Clad. Using a other alternatives to achieving higher power dissipation from board material such as Thermal Clad, an aluminum core the surface mount packages. One is to increase the area of the board, the power dissipation can be doubled using the same drain pad. By increasing the area of the drain pad, the power footprint. Motorola TMOS Power MOSFET Transistor Device Data 7
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total between the board and the package. With the correct pad design. The footprint for the semiconductor packages must be geometry, the packages will self align when subjected to a the correct size to ensure proper solder connection interface solder reflow process. 0.165 0.118 4.191 3.0 0.100 2.54 0.063 1.6 0.190 0.243 4.826 6.172 inches mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a dissipation can be increased. Although one can almost double function of the drain pad size. These can vary from the the power dissipation with this method, one will be giving up minimum pad size for soldering to a pad size given for area on the printed circuit board which can defeat the purpose maximum power dissipation. Power dissipation for a surface of using surface mount technology. For example, a graph of mount device is determined by TJ(max), the maximum rated RθJA versus drain pad area is shown in Figure 15. junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating 100 temperature, T Board Material = 0.0625″ A. Using the values provided on the data sheet, G−10/FR−4, 2 oz Copper PD can be calculated as follows: 1.75 Watts 80 T TA = 25°C P J(max) − TA D = C/W) ANCE, JUNCTION ° Rθ ( JA 60 The values for the equation are found in the maximum RESIST 3.0 Watts AMBIENT ratings table on the data sheet. Substituting these values into TO the equation for an ambient temperature T 40 A of 25°C, one can 5.0 Watts calculate the power dissipation of the device. For a DPAK , THERMAL device, P JAθ D is calculated as follows. R 200 2 4 6 8 10 150°C − 25°C PD = = 1.75 Watts A, AREA (SQUARE INCHES) 71.4°C/W
Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)
The 71.4°C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit Another alternative would be to use a ceramic substrate or board to achieve a power dissipation of 1.75 Watts. There are an aluminum core board such as Thermal Clad. Using a other alternatives to achieving higher power dissipation from board material such as Thermal Clad, an aluminum core the surface mount packages. One is to increase the area of the board, the power dissipation can be doubled using the same drain pad. By increasing the area of the drain pad, the power footprint. Motorola TMOS Power MOSFET Transistor Device Data 7
