Datasheet SSM2604 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Low Power Audio Codec |
| Pages / Page | 28 / 5 — Data Sheet. SSM2604. TIMING CHARACTERISTICS. Table 3. I2C Timing. Limit. … |
| Revision | B |
| File Format / Size | PDF / 443 Kb |
| Document Language | English |
Data Sheet. SSM2604. TIMING CHARACTERISTICS. Table 3. I2C Timing. Limit. Parameter. tMIN. tMAX. Unit. Description. tSCH. tHCS. SDIN. SCS. SCLK. tRT
Model Line for this Datasheet
Text Version of Document
Data Sheet SSM2604 TIMING CHARACTERISTICS Table 3. I2C Timing Limit Parameter tMIN tMAX Unit Description
tSCS 600 ns Start condition setup time tSCH 600 ns Start condition hold time tPH 600 ns SCLK pulse width high tPL 1.3 µs SCLK pulse width low fSCLK 0 526 kHz SCLK frequency tDS 100 ns Data setup time tDH 900 ns Data hold time tRT 300 ns SDIN and SCLK rise time tFT 300 ns SDIN and SCLK fall time tHCS 600 ns Stop condition setup time
tSCH tHCS SDIN t t t DS t SCS PL PH
036
SCLK tRT tDH tFT
06978- Figure 2. I2C Timing
Table 4. Digital Audio Interface Slave Mode Timing Limit Parameter tMIN tMAX Unit Description
tDS 10 ns PBDAT setup time from BCLK rising edge tDH 10 ns PBDAT hold time from BCLK rising edge tLRSU 10 ns RECLRC/PBLRC setup time to BCLK rising edge tLRH 10 ns RECLRC/PBLRC hold time to BCLK rising edge tDD 30 ns RECDAT propagation delay from BCLK falling edge (external load of 70 pF) tBCH 25 ns BCLK pulse width high tBCL 25 ns BCLK pulse width low tBCY 50 ns BCLK cycle time
t t BCH BCL BCLK tBCY PBLRC/ RECLRC tDS t t LRH LRSU PBDAT tDH tDD
025
RECDAT
06978- Figure 3. Digital Audio Interface Slave Mode Timing Rev. B | Page 5 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Digital Filter Characteristics Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Converter Filter Response Digital De-Emphasis Theory of Operation Digital Core ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Analog Interface Signal Chain Stereo Line Inputs Bypass Path to Output Line Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Software Control Interface Control Register Sequencing Typical Application Circuits Register Map Register Map Details Left-Channel ADC Input Volume, Address 0x00 Right-Channel ADC Input Volume, Address 0x01 Analog Audio Path, Address 0x04 Digital Audio Path, Address 0x05 Power Management, Address 0x06 Power Consumption Digital Audio I/F, Address 0x07 Sampling Rate, Address 0x08 Active, Address 0x09 Software Reset, Address 0x0F Outline Dimensions Ordering Guide
tSCS 600 ns Start condition setup time tSCH 600 ns Start condition hold time tPH 600 ns SCLK pulse width high tPL 1.3 µs SCLK pulse width low fSCLK 0 526 kHz SCLK frequency tDS 100 ns Data setup time tDH 900 ns Data hold time tRT 300 ns SDIN and SCLK rise time tFT 300 ns SDIN and SCLK fall time tHCS 600 ns Stop condition setup time
tSCH tHCS SDIN t t t DS t SCS PL PH
036
SCLK tRT tDH tFT
06978- Figure 2. I2C Timing
Table 4. Digital Audio Interface Slave Mode Timing Limit Parameter tMIN tMAX Unit Description
tDS 10 ns PBDAT setup time from BCLK rising edge tDH 10 ns PBDAT hold time from BCLK rising edge tLRSU 10 ns RECLRC/PBLRC setup time to BCLK rising edge tLRH 10 ns RECLRC/PBLRC hold time to BCLK rising edge tDD 30 ns RECDAT propagation delay from BCLK falling edge (external load of 70 pF) tBCH 25 ns BCLK pulse width high tBCL 25 ns BCLK pulse width low tBCY 50 ns BCLK cycle time
t t BCH BCL BCLK tBCY PBLRC/ RECLRC tDS t t LRH LRSU PBDAT tDH tDD
025
RECDAT
06978- Figure 3. Digital Audio Interface Slave Mode Timing Rev. B | Page 5 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Digital Filter Characteristics Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Converter Filter Response Digital De-Emphasis Theory of Operation Digital Core ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Analog Interface Signal Chain Stereo Line Inputs Bypass Path to Output Line Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Software Control Interface Control Register Sequencing Typical Application Circuits Register Map Register Map Details Left-Channel ADC Input Volume, Address 0x00 Right-Channel ADC Input Volume, Address 0x01 Analog Audio Path, Address 0x04 Digital Audio Path, Address 0x05 Power Management, Address 0x06 Power Consumption Digital Audio I/F, Address 0x07 Sampling Rate, Address 0x08 Active, Address 0x09 Software Reset, Address 0x0F Outline Dimensions Ordering Guide
