Datasheet SSM2604 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Low Power Audio Codec |
| Pages / Page | 28 / 6 — SSM2604. Data Sheet. Table 5. Digital Audio Interface Master Mode Timing. … |
| Revision | B |
| File Format / Size | PDF / 443 Kb |
| Document Language | English |
SSM2604. Data Sheet. Table 5. Digital Audio Interface Master Mode Timing. Limit. Parameter. tMIN. tMAX. Unit. Description. BCLK. tDL. PBLRC/
Model Line for this Datasheet
Text Version of Document
SSM2604 Data Sheet Table 5. Digital Audio Interface Master Mode Timing Limit Parameter tMIN tMAX Unit Description
tDST 30 ns PBDAT setup time to BCLK rising edge tDHT 10 ns PBDAT hold time to BCLK rising edge tDL 10 ns RECLRC/PBLRC propagation delay from BCLK falling edge tDDA 10 ns RECDAT propagation delay from BCLK falling edge tBCLKR 10 ns BCLK rising time (10 pF load) tBCLKF 10 ns BCLK falling time (10 pF load) tBCLKDS 45:55:00 55:45:00 BCLK duty cycle (normal and USB mode)
BCLK tDL PBLRC/ RECLRC tDST tDHT PBDAT tDDA
026
RECDAT
06978- Figure 4. Digital Audio Interface Master Mode Timing
Table 6. System Clock Timing Limit Parameter tMIN tMAX Unit Description
tXTIY 72 ns MCLK/XTI system clock cycle time tMCLKDS 40:60 60:40:00 MCLK/XTI duty cycle tXTIH 32 ns MCLK/XTI system clock pulse width high tXTIL 32 ns MCLK/XTI system clock pulse width low tCOP 20 ns CLKOUT propagation delay from MCLK/XTI falling edge tCOPDIV2 20 ns CLKODIV2 propagation delay from MCLK/XTI falling edge
tXTIH tCOP MCLK/XTI tXTIL tXTIY CLKOUT CLKODIV2
035
tCOPDIV2
06978- Figure 5. System (MCLK) Clock Timing Rev. B | Page 6 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Digital Filter Characteristics Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Converter Filter Response Digital De-Emphasis Theory of Operation Digital Core ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Analog Interface Signal Chain Stereo Line Inputs Bypass Path to Output Line Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Software Control Interface Control Register Sequencing Typical Application Circuits Register Map Register Map Details Left-Channel ADC Input Volume, Address 0x00 Right-Channel ADC Input Volume, Address 0x01 Analog Audio Path, Address 0x04 Digital Audio Path, Address 0x05 Power Management, Address 0x06 Power Consumption Digital Audio I/F, Address 0x07 Sampling Rate, Address 0x08 Active, Address 0x09 Software Reset, Address 0x0F Outline Dimensions Ordering Guide
tDST 30 ns PBDAT setup time to BCLK rising edge tDHT 10 ns PBDAT hold time to BCLK rising edge tDL 10 ns RECLRC/PBLRC propagation delay from BCLK falling edge tDDA 10 ns RECDAT propagation delay from BCLK falling edge tBCLKR 10 ns BCLK rising time (10 pF load) tBCLKF 10 ns BCLK falling time (10 pF load) tBCLKDS 45:55:00 55:45:00 BCLK duty cycle (normal and USB mode)
BCLK tDL PBLRC/ RECLRC tDST tDHT PBDAT tDDA
026
RECDAT
06978- Figure 4. Digital Audio Interface Master Mode Timing
Table 6. System Clock Timing Limit Parameter tMIN tMAX Unit Description
tXTIY 72 ns MCLK/XTI system clock cycle time tMCLKDS 40:60 60:40:00 MCLK/XTI duty cycle tXTIH 32 ns MCLK/XTI system clock pulse width high tXTIL 32 ns MCLK/XTI system clock pulse width low tCOP 20 ns CLKOUT propagation delay from MCLK/XTI falling edge tCOPDIV2 20 ns CLKODIV2 propagation delay from MCLK/XTI falling edge
tXTIH tCOP MCLK/XTI tXTIL tXTIY CLKOUT CLKODIV2
035
tCOPDIV2
06978- Figure 5. System (MCLK) Clock Timing Rev. B | Page 6 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Digital Filter Characteristics Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Converter Filter Response Digital De-Emphasis Theory of Operation Digital Core ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Analog Interface Signal Chain Stereo Line Inputs Bypass Path to Output Line Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Software Control Interface Control Register Sequencing Typical Application Circuits Register Map Register Map Details Left-Channel ADC Input Volume, Address 0x00 Right-Channel ADC Input Volume, Address 0x01 Analog Audio Path, Address 0x04 Digital Audio Path, Address 0x05 Power Management, Address 0x06 Power Consumption Digital Audio I/F, Address 0x07 Sampling Rate, Address 0x08 Active, Address 0x09 Software Reset, Address 0x0F Outline Dimensions Ordering Guide
