Datasheet AD7294-2 (Analog Devices) - 7

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Data Sheet AD7294-2 GENERAL SPECIFICATIONS
AVDD = 4.5 V to 5.5 V, AGND1 to AGND7 = DGND = 0 V, internal or external 2.5 V reference; VDRIVE = 2.7 V to 5.5 V; VPPx = AVDD to 59.4 V; DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating; therefore, DAC output span = 0 V to 5 V; TA = −40°C to +105°C, unless otherwise noted.
Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS Input High Voltage VIH 0.7 VDRIVE V SDA, SCL only Input Low Voltage VIL 0.3 VDRIVE V SDA, SCL only Input Leakage Current IIN ±1 µA Input Hysteresis1 VHYST 0.05 VDRIVE V Input Capacitance1 CIN 8 pF Glitch Rejection1 50 ns Input filtering suppresses noise spikes of less than 50 ns Maximum External Capacitance of 30 pF Tristate input I2C Address Pins When Floating1 LOGIC OUTPUTS SDA, ALERT SDA and ALERT/BUSY are open-drain outputs Output Low Voltage VOL 0.4 V ISINK = 3 mA 0.6 V ISINK = 6 mA Floating-State Leakage Current1 ±1 µA Floating-State Output 8 pF Capacitance1 ISENSE OVERRANGE ISENSEx OVERRANGE are push-pull outputs Output High Voltage VOH VDRIVE − 0.2 V ISOURCE = 200 µA for push-pull outputs Output Low Voltage VOL 0.2 V ISINK = 200 µA for push-pull outputs Overrange Setpoint1 VFS VFS × 1.2 mV VFS = ±VREF ADC/12.5 POWER REQUIREMENTS VPP1, VPP2 AVDD 59.4 V AVDD 4.5 5.5 V DAC OUTV+ xx 4.5 16.5 V VDRIVE 2.7 5.5 V IDD 5.3 7.5 mA AVDD + VDRIVE; DAC outputs unloaded DAC OUTV+ xx, IDD 0.6 1.2 mA At midscale output voltage, DAC outputs unloaded Power Dissipation 70 110 mW Power-Down IDD 4.4 5.5 mA AVDD and VDRIVE; ADC, DACs, and temperature sensor powered down DAC OUTV+ x, IDD 35 60 µA Power Dissipation 70 mW 1 Guaranteed by design and characterization; not production tested. Rev. 0 | Page 7 of 44 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications DAC Specifications ADC Specifications General Specifications Timing Characteristics I2C Serial Interface Timing and Circuit Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology DAC Terminology ADC Terminology Theory of Operation ADC Overview ADC Transfer Functions Analog Inputs Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode Current Sensor Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection Analog Comparator Loop Temperature Sensor Remote Sensing Diode Ideality Factor Base Emitter Voltage hFE Variation Series Resistance Cancellation DAC Operation Resistor String Output Amplifiers ADC and DAC Reference VDRIVE Feature Register Settings Address Pointer Register Command Register ADC Result Register ADC Channel Allocation TSENSE1 and TSENSE2 Result Registers TSENSEINT Result Register Temperature Value Format DACA, DACB, DACC, and DACD Value Registers Alert Status Register A, Alert Status Register B, and Alert Status Register C Channel Sequence Register Configuration Register Sample Delay and Bit Trial Delay Power-Down Register DATALOW and DATAHIGH Registers VIN0 to VIN3 Channels TSENSE1, TSENSE2, and TSENSEINT Channels Hysteresis Registers Remote Channel TSENSE1 and TSENSE2 Offset Registers I2C Interface General I2C Timing Serial Bus Address Byte Interface Protocol Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register Modes of Operation Command Mode Autocycle Mode Alerts and Limits Theory ALERT_FLAG Bit Alert Status Registers DATALOW and DATAHIGH Monitoring Features Hysteresis Using the Limit Registers to Store Minimum/Maximum Conversion Results Applications Information Base Station Power Amplifier Monitor and Control Gain Control of Power Amplifier Outline Dimensions Ordering Guide