Datasheet AD7294-2 (Analog Devices) - 9

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Data Sheet AD7294-2 ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.1 Stresses above those listed under Absolute Maximum Ratings
Table 5.
may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any
Parameter Rating
other conditions above those indicated in the operational VPPx to AGND −0.3 V to +65 V section of this specification is not implied. Exposure to absolute AVDD to AGND −0.3 V to +7 V maximum rating conditions for extended periods may affect DAC OUTV+ AB to AGND −0.3 V to +17 V device reliability. DAC OUTV+ CD to AGND −0.3 V to +17 V V To conform with IPC-2221 industrial standards, it is advisable DRIVE to OPGND −0.3 V to +7 V Digital Inputs to OPGND −0.3 V to V to use conformal coating on the high voltage pins. DRIVE + 0.3 V RESET to OPGND −0.3 V to +7 V
THERMAL RESISTANCE
SDA/SCL to OPGND −0.3 V to +7 V Digital Outputs to OPGND −0.3 V to VDRIVE + 0.3 V
Table 6. Thermal Resistance
RS(+)/RS(−) to VPPx VPPx − 0.3 V to VPPx + 0.3 V
Package Type θJA θJC Unit
REFOUT/REFIN ADC to AGND −0.3 V to AVDD + 0.3 V 64-Lead TQFP 54 16 °C/W REFOUT/REFIN DAC to AGND −0.3 V to AVDD + 0.3 V OPGND to AGND −0.3 V to +0.3 V
ESD CAUTION
OPGND to DGND −0.3 V to +0.3 V AGND to DGND −0.3 V to +0.3 V VOUTx to AGND −0.3 V to DAC OUTV+ xx + 0.3 V Analog Inputs to AGND −0.3 V to AVDD + 0.3 V Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ MAX) 150°C ESD, Human Body Model 1 kV Reflow Soldering Peak 260°C Temperature 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. 0 | Page 9 of 44 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications DAC Specifications ADC Specifications General Specifications Timing Characteristics I2C Serial Interface Timing and Circuit Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology DAC Terminology ADC Terminology Theory of Operation ADC Overview ADC Transfer Functions Analog Inputs Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode Current Sensor Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection Analog Comparator Loop Temperature Sensor Remote Sensing Diode Ideality Factor Base Emitter Voltage hFE Variation Series Resistance Cancellation DAC Operation Resistor String Output Amplifiers ADC and DAC Reference VDRIVE Feature Register Settings Address Pointer Register Command Register ADC Result Register ADC Channel Allocation TSENSE1 and TSENSE2 Result Registers TSENSEINT Result Register Temperature Value Format DACA, DACB, DACC, and DACD Value Registers Alert Status Register A, Alert Status Register B, and Alert Status Register C Channel Sequence Register Configuration Register Sample Delay and Bit Trial Delay Power-Down Register DATALOW and DATAHIGH Registers VIN0 to VIN3 Channels TSENSE1, TSENSE2, and TSENSEINT Channels Hysteresis Registers Remote Channel TSENSE1 and TSENSE2 Offset Registers I2C Interface General I2C Timing Serial Bus Address Byte Interface Protocol Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register Modes of Operation Command Mode Autocycle Mode Alerts and Limits Theory ALERT_FLAG Bit Alert Status Registers DATALOW and DATAHIGH Monitoring Features Hysteresis Using the Limit Registers to Store Minimum/Maximum Conversion Results Applications Information Base Station Power Amplifier Monitor and Control Gain Control of Power Amplifier Outline Dimensions Ordering Guide