Datasheet ADRV9008-2 (Analog Devices) - 6

link to page 67 link to page 12
ADRV9008-2 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Third-Order IM3 −70 dBc 2 × GSMK carriers, ΣPOUT = Intermodulation −12 dBFS rms The two carriers can be placed anywhere within the transmitter band such that the IM3 products fall within the transmitter band or within 10 MHz of the band edges Carrier Leakage With LO leakage correction active, 0 dB attenuation, scales decibel for decibel with attenuation, measured in 1 MHz bandwidth, resolution bandwidth, and video bandwidth = 100 kHz, rms detector, 100 trace average Carrier Offset from −84 dBFS 75 MHz < f ≤ 600 MHz Local Oscillator (LO) −82 dBFS 600 MHz < f ≤ 4800 MHz −80 dBFS 4800 MHz < f ≤ 6000 MHz Carrier on LO −71 dBFS Error Vector Magnitude EVM (Third Generation Partnership Project (3GPP) Test Signals) 75 MHz LO2 0.5 % 300 kHz RF PLL loop bandwidth 1900 MHz LO 0.7 % 50 kHz RF PLL loop bandwidth 3800 MHz LO 0.7 % 300 kHz RF PLL loop bandwidth 5900 MHz LO 1.1 % 300 kHz RF PLL loop bandwidth Output Impedance ZOUT 50 Ω Differential (see Figure 265) OBSERVATION RECEIVER ORx Center Frequency 75 6000 MHz Gain Range 30 dB Third-order input intermodulation intercept point (I P3) improves decibel for decibel for the first 18 dB of gain attenuation, QEC performance optimized for 0 dB to 6 dB of attenuation only Analog Gain Step 0.5 dB For attenuator steps from 0 dB to 6 dB Peak-to-Peak Gain 1 dB 450 MHz bandwidth, compensated Deviation by programmable FIR filter Gain Slope ±0.1 dB Any 20 MHz bandwidth span, compensated by programmable FIR filter Deviation from Linear 1 Degrees 450 MHz RF bandwidth Phase Observation Receiver 450 MHz Bandwidth Observation Receiver 60 dB Due to digital filters Alias Band Rejection Maximum Useable Input PHIGH 0 dB attenuation, increases decibel Level for decibel with attenuation, continuous wave corresponds to −1 dBFS at ADC −11 dBm 75 MHz < f ≤ 3000 MHz −9.5 dBm 3000 MHz < f ≤ 4800 MHz −8 dBm 4800 MHz < f ≤ 6000 MHz Integrated Noise −58.5 dBFS 450 MHz integration bandwidth −57.5 dBFS 491.52 MHz integration bandwidth Rev. 0 | Page 6 of 95 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Transmitter Output Impedance Observation Receiver Input Impedance Terminology Theory of Operation Transmitter Observation Receiver Clock Input Synthesizers RF PLL Clock PLL Serial Peripheral Interface (SPI) JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines Transmitter Balun DC Feed Supplies JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-2W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File Transmitter Bias and Port Interface General Observation Receiver Path Interface Impedance Matching Network Example Outline Dimensions Ordering Guide