Datasheet ADRV9008-1 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Integrated Dual RF Receiver |
| Pages / Page | 68 / 10 — ADRV9008-1. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 3. Parameter. … |
| File Format / Size | PDF / 1.9 Mb |
| Document Language | English |
ADRV9008-1. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 3. Parameter. Rating. THERMAL RESISTANCE. Table 4. Thermal Resistance1, 2
Model Line for this Datasheet
Text Version of Document
link to page 10 link to page 10 link to page 10 link to page 10
ADRV9008-1 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3.
exposed die package to provide the customer with the most
Parameter Rating
effective method of controlling the die temperature. The exposed die allows cooling of the die directly. Figure 4 shows the profile VDDA1P31 to VSSA −0.3 V to +1.4 V view of the device mounted to a user printed circuit board (PCB) VDDD1P3_DIG to VSSD −0.3 V to +1.4 V and a heat sink (typical y the aluminum case) to keep the junction VDD_INTERFACE to VSSA −0.3 V to +3.0 V (exposed die) below the maximum junction temperature shown VDDA_3P3 to VSSA −0.3 V to +3.9 V in Table 3. The device is designed for a lifetime of 10 years when VDD_INTERFACE Logic Inputs and −0.3 V to VDD_ Outputs to VSSD INTERFACE + 0.3 V operating at the maximum junction temperature. JESD204B Logic Outputs to VSSA −0.3 V to VDDA1P3_SER
THERMAL RESISTANCE
Input Current to Any Pin Except ±10 mA θ Supplies JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Thermal Maximum Input Power into RF Port 23 dBm (peak) resistance data for the ADRV9008-1 mounted on both a JEDEC Maximum Junction Temperature 110°C 2S2P test board and a 10-layer Analog Devices, Inc., evaluation Storage Temperature Range −65°C to +150°C board is listed in Table 4. Do not exceed the absolute maximum 1 VDDA1P3 refers to all analog 1.3 V supplies, including VDDA1P3_RF_SYNTH, junction temperature rating in Table 3. Ten-layer PCB entries VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX, VDDA1P3_RF_VCO_LDO, refer to the 10-layer Analog Devices evaluation board, which VDDA1P3_RF_LO, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_SYNTH, and VDDA1P3_CLOCK_VCO_LDO. more accurately reflects the PCB used in customer applications. Stresses at or above those listed under Absolute Maximum
Table 4. Thermal Resistance1, 2
Ratings may cause permanent damage to the product. This is a
Package Type θ θ θ Ψ Ψ Unit
stress rating only; functional operation of the product at these
JA JC_TOP JB JT JB
BC-196-13 21.1 0.04 4.9 0.3 4.9
°
C/W or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond 1 For the θJC test, 100 µm thermal interface material (TIM) is used. TIM is assumed to have 3.6 thermal conductivity watts/(meter × Kelvin). the maximum operating conditions for extended periods may 2 Using enhanced heat removal techniques such as PCB, heat sink, and airflow affect product reliability. improves the thermal resistance values.
REFLOW PROFILE
The ADRV9008-1 reflow profile is in accordance with the
ESD CAUTION
JEDEC JESD204B criteria for Pb-free devices. The maximum reflow temperature is 260°C.
THERMAL MANAGEMENT
The ADRV9008-1 is a high power device that can dissipate over 3 W depending on the user application and configuration. Because of the power dissipation, the ADRV9008-1 uses an
CUSTOMER CASE (HEAT SINK) CUSTOMER THERMAL FILLER SILICON (DIE) IC PROFILE PACKAGE SUBSTRATE
008
CUSTOMER PCB
16830- Figure 4. Typical Thermal Management Solution Rev. 0 | Page 10 of 68 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Receiver Input Impedance Terminology Theory of Operation Receivers Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-1W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide
ADRV9008-1 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3.
exposed die package to provide the customer with the most
Parameter Rating
effective method of controlling the die temperature. The exposed die allows cooling of the die directly. Figure 4 shows the profile VDDA1P31 to VSSA −0.3 V to +1.4 V view of the device mounted to a user printed circuit board (PCB) VDDD1P3_DIG to VSSD −0.3 V to +1.4 V and a heat sink (typical y the aluminum case) to keep the junction VDD_INTERFACE to VSSA −0.3 V to +3.0 V (exposed die) below the maximum junction temperature shown VDDA_3P3 to VSSA −0.3 V to +3.9 V in Table 3. The device is designed for a lifetime of 10 years when VDD_INTERFACE Logic Inputs and −0.3 V to VDD_ Outputs to VSSD INTERFACE + 0.3 V operating at the maximum junction temperature. JESD204B Logic Outputs to VSSA −0.3 V to VDDA1P3_SER
THERMAL RESISTANCE
Input Current to Any Pin Except ±10 mA θ Supplies JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Thermal Maximum Input Power into RF Port 23 dBm (peak) resistance data for the ADRV9008-1 mounted on both a JEDEC Maximum Junction Temperature 110°C 2S2P test board and a 10-layer Analog Devices, Inc., evaluation Storage Temperature Range −65°C to +150°C board is listed in Table 4. Do not exceed the absolute maximum 1 VDDA1P3 refers to all analog 1.3 V supplies, including VDDA1P3_RF_SYNTH, junction temperature rating in Table 3. Ten-layer PCB entries VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX, VDDA1P3_RF_VCO_LDO, refer to the 10-layer Analog Devices evaluation board, which VDDA1P3_RF_LO, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_SYNTH, and VDDA1P3_CLOCK_VCO_LDO. more accurately reflects the PCB used in customer applications. Stresses at or above those listed under Absolute Maximum
Table 4. Thermal Resistance1, 2
Ratings may cause permanent damage to the product. This is a
Package Type θ θ θ Ψ Ψ Unit
stress rating only; functional operation of the product at these
JA JC_TOP JB JT JB
BC-196-13 21.1 0.04 4.9 0.3 4.9
°
C/W or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond 1 For the θJC test, 100 µm thermal interface material (TIM) is used. TIM is assumed to have 3.6 thermal conductivity watts/(meter × Kelvin). the maximum operating conditions for extended periods may 2 Using enhanced heat removal techniques such as PCB, heat sink, and airflow affect product reliability. improves the thermal resistance values.
REFLOW PROFILE
The ADRV9008-1 reflow profile is in accordance with the
ESD CAUTION
JEDEC JESD204B criteria for Pb-free devices. The maximum reflow temperature is 260°C.
THERMAL MANAGEMENT
The ADRV9008-1 is a high power device that can dissipate over 3 W depending on the user application and configuration. Because of the power dissipation, the ADRV9008-1 uses an
CUSTOMER CASE (HEAT SINK) CUSTOMER THERMAL FILLER SILICON (DIE) IC PROFILE PACKAGE SUBSTRATE
008
CUSTOMER PCB
16830- Figure 4. Typical Thermal Management Solution Rev. 0 | Page 10 of 68 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Receiver Input Impedance Terminology Theory of Operation Receivers Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-1W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide
