Datasheet AD9363 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | RF Agile Transceiver |
| Pages / Page | 32 / 1 — RF Agile Transceiver. Data Sheet. AD9363. FEATURES. FUNCTIONAL BLOCK … |
| Revision | D |
| File Format / Size | PDF / 529 Kb |
| Document Language | English |
RF Agile Transceiver. Data Sheet. AD9363. FEATURES. FUNCTIONAL BLOCK DIAGRAM
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RF Agile Transceiver Data Sheet AD9363 FEATURES FUNCTIONAL BLOCK DIAGRAM Radio frequency (RF) 2 × 2 transceiver with integrated 12-bit RX1B_P, RX1B_N AD9363 DACs and ADCs RX1A_P, ADC Wide bandwidth: 325 MHz to 3.8 GHz RX1A_N Supports time division duplex (TDD) and frequency division RX1C_P, RX1C_N duplex (FDD) operation RX2B_P, RX2B_N Tunable channel bandwidth (BW): up to 20 MHz P0_D11/ RX2A_P, ADC TX_D5_x TO P0_D0/ Receivers: 6 differential or 12 single-ended inputs RX2A_N ACE TX_D0_x RX2C_P, Superior receiver sensitivity with a noise figure: 3 dB RF RX2C_N RX LO E Receive (Rx) gain control NT TX_MON1 TX LO A I Real-time monitor and control signals for manual gain TX1A_P, P1_D11/ DAC DAT RX_D5_x TO P1_D0/ Independent automatic gain control (AGC) TX1A_N RX_D0_x TX1B_P, Dual transmitters: 4 differential outputs TX1B_N Highly linear broadband transmitter TX_MON2 Transmit (Tx) error vector magnitude (EVM): −34 dB TX2A_P, DAC TX2A_N Tx noise: ≤−157 dBm/Hz noise floor TX2B_P, RADIO Tx monitor: 66 dB dynamic range with 1 dB accuracy TX2B_N GPO SWITCHING ADC DAC DAC Integrated fractional N synthesizers SPI CTRL PLLs CLK_OUT 2.4 Hz local oscillator (LO) step size CTRL CMOS/LVDS digital interface AUXADC AUXDACx XTALN APPLICATIONS NOTES 1. SPI, CTRL, P0_D11/TX_D5_x TO P0_D0/TX_D0_x, P1_D11/
001
RX_D5_x TO P1_D0/RX_D0_x, AND RADIO SWITCHING 3G enterprise femtocell base stations CONTAIN MULTIPLE PINS.
10558-
4G femtocell base stations
Figure 1.
Wireless video transmission GENERAL DESCRIPTION
The AD9363 is a high performance, highly integrated RF agile sample rate. transceiver designed for use in 3G and 4G femtocell applications. The transmitters use a direct conversion architecture that achieves Its programmability and wideband capability make it ideal for a high modulation accuracy with ultralow noise. This transmitter broad range of transceiver applications. The device combines an design produces a best-in-class Tx EVM of −34 dB, allowing RF front end with a flexible mixed-signal baseband section and significant system margin for the external power amplifier (PA) integrated frequency synthesizers, simplifying design-in by selection. The on-board Tx power monitor can be used as a providing a configurable digital interface to a processor. The power detector, enabling highly accurate Tx power AD9363 operates in the 325 MHz to 3.8 GHz range, covering measurements. most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 20 MHz are supported. The fully integrated phase-locked loops (PLLs) provide low power fractional N frequency synthesis for al receive and The two independent direct conversion receivers have state-of- transmit channels. Channel isolation, demanded by FDD the-art noise figure and linearity. Each Rx subsystem includes systems, is integrated into the design. All voltage control ed independent automatic gain control (AGC), dc offset correction, oscillators (VCOs) and loop filter components are integrated. quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband. The AD9363 The core of the AD9363 can be powered directly from a 1.3 V also has flexible manual gain modes that can be externally regulator. The IC is control ed via a standard 4-wire serial port controlled. Two high dynamic range ADCs per channel digitize and four real-time I/O control pins. Comprehensive power-down the received I and Q signals and pass them through configurable modes are included to minimize power consumption during decimation filters and 128-tap finite impulse response (FIR) normal use. The AD9363 is packaged in a 10 mm × 10 mm, filters to produce a 12-bit output signal at the appropriate 144-ball chip scale package ball grid array (CSP_BGA).
Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHZ FREQUENCY BAND 2.4 GHZ FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME and TX_FRAME Signals ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9363 APPLICATIONS INFORMATION PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
001
RX_D5_x TO P1_D0/RX_D0_x, AND RADIO SWITCHING 3G enterprise femtocell base stations CONTAIN MULTIPLE PINS.
10558-
4G femtocell base stations
Figure 1.
Wireless video transmission GENERAL DESCRIPTION
The AD9363 is a high performance, highly integrated RF agile sample rate. transceiver designed for use in 3G and 4G femtocell applications. The transmitters use a direct conversion architecture that achieves Its programmability and wideband capability make it ideal for a high modulation accuracy with ultralow noise. This transmitter broad range of transceiver applications. The device combines an design produces a best-in-class Tx EVM of −34 dB, allowing RF front end with a flexible mixed-signal baseband section and significant system margin for the external power amplifier (PA) integrated frequency synthesizers, simplifying design-in by selection. The on-board Tx power monitor can be used as a providing a configurable digital interface to a processor. The power detector, enabling highly accurate Tx power AD9363 operates in the 325 MHz to 3.8 GHz range, covering measurements. most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 20 MHz are supported. The fully integrated phase-locked loops (PLLs) provide low power fractional N frequency synthesis for al receive and The two independent direct conversion receivers have state-of- transmit channels. Channel isolation, demanded by FDD the-art noise figure and linearity. Each Rx subsystem includes systems, is integrated into the design. All voltage control ed independent automatic gain control (AGC), dc offset correction, oscillators (VCOs) and loop filter components are integrated. quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband. The AD9363 The core of the AD9363 can be powered directly from a 1.3 V also has flexible manual gain modes that can be externally regulator. The IC is control ed via a standard 4-wire serial port controlled. Two high dynamic range ADCs per channel digitize and four real-time I/O control pins. Comprehensive power-down the received I and Q signals and pass them through configurable modes are included to minimize power consumption during decimation filters and 128-tap finite impulse response (FIR) normal use. The AD9363 is packaged in a 10 mm × 10 mm, filters to produce a 12-bit output signal at the appropriate 144-ball chip scale package ball grid array (CSP_BGA).
Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHZ FREQUENCY BAND 2.4 GHZ FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME and TX_FRAME Signals ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9363 APPLICATIONS INFORMATION PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
