Datasheet AD9363 (Analog Devices) - 8

AD9363 Data Sheet CURRENT CONSUMPTION—VDD_INTERFACE Table 3. VDD_INTERFACE = 1.2 V Parameter Min Typ Max Unit Test Conditions/Comments
SLEEP MODE 45 μA Power applied, device disabled ONE Rx CHANNEL, ONE Tx CHANNEL, DOUBLE DATA RATE (DDR) LTE10 Single Port 2.9 mA 30.72 MHz data clock, CMOS Dual Port 2.7 mA 15.36 MHz data clock, CMOS LTE20 Dual Port 5.2 mA 30.72 MHz data clock, CMOS TWO Rx CHANNELS, TWO Tx CHANNELS, DDR LTE3 Dual Port 1.3 mA 7.68 MHz data clock, CMOS LTE10 Single Port 4.6 mA 61.44 MHz data clock, CMOS Dual Port 5.0 mA 30.72 MHz data clock, CMOS LTE20 Dual Port 8.2 mA 61.44 MHz data clock, CMOS GSM Dual Port 0.2 mA 1.08 MHz data clock, CMOS WiMAX 8.75 MHz Dual Port 3.3 mA 20 MHz data clock, CMOS WiMAX 10 MHz Single Port TDD Rx 0.5 mA 22.4 MHz data clock, CMOS TDD Tx 3.6 mA 22.4 MHz data clock, CMOS FDD 3.8 mA 44.8 MHz data clock, CMOS WiMAX 20 MHz Dual Port FDD 6.7 mA 44.8 MHz data clock, CMOS Rev. D | Page 8 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHZ FREQUENCY BAND 2.4 GHZ FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME and TX_FRAME Signals ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9363 APPLICATIONS INFORMATION PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE