Datasheet AD9361 (Analog Devices) - 16
| Manufacturer | Analog Devices |
| Description | RF Agile Transceiver |
| Pages / Page | 36 / 16 — AD9361. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. … |
| Revision | F |
| File Format / Size | PDF / 648 Kb |
| Document Language | English |
AD9361. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. VDDA1P1_. TX_EXT_. RX2A_N. RX2A_P. VSSA. TX_MON2. TX2A_N. TX2A_P. TX2B_N
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AD9361 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 VDDA1P1_ TX_EXT_ A RX2A_N RX2A_P NC VSSA TX_MON2 VSSA TX2A_N TX2A_P TX2B_N TX2B_P TX_VCO LO_IN VDDA1P3_ VDDA1P3_ TX_VCO_ B VSSA VSSA AUXDAC1 GPO_3 GPO_2 GPO_1 GPO_0 VDD_GPO TX_VCO_ VSSA TX_LO LDO_OUT LDO TEST/ C RX2C_P VSSA AUXDAC2 ENABLE CTRL_IN0 CTRL_IN1 VSSA VSSA VSSA VSSA VSSA VSSA VDDA1P3_ VDDA1P3_ P0_D9/ P0_D7/ P0_D5/ P0_D3/ P0_D1/ RX2C_N CTRL_OUT0 CTRL_IN3 CTRL_IN2 VSSD D RX_RF RX_TX TX_D4_P TX_D3_P TX_D2_P TX_D1_P TX_D0_P VDDA1P3_ VDDA1P3_ P0_D11/ P0_D8/ P0_D6/ P0_D4/ P0_D2/ P0_D0/ E RX2B_P TX_LO_ CTRL_OUT1 CTRL_OUT2 CTRL_OUT3 RX_LO TX_D5_P TX_D4_N TX_D3_N TX_D2_N TX_D1_N TX_D0_N BUFFER VDDA1P3_ P0_D10/ VDDD1P3_ F RX2B_N RX_VCO_ VSSA CTRL_OUT6 CTRL_OUT5 CTRL_OUT4 VSSD TX_D5_N VSSD FB_CLK_P VSSD DIG LDO RX_EXT_ RX_VCO_ VDDA1P1_ RX_ RX_ TX_ DATA_ G CTRL_OUT7 EN_AGC ENABLE FB_CLK_N VSSD LO_IN LDO_OUT RX_VCO FRAME_N FRAME_P FRAME_P CLK_P P1_D11/ TX_ DATA_ VDD_ H RX1B_P VSSA VSSA TXNRX SYNC_IN VSSA VSSD VSSD RX_D5_P FRAME_N CLK_N INTERFACE VDDA1P3_ P1_D10/ P1_D9/ P1_D7/ P1_D5/ P1_D3/ P1_D1/ J RX1B_N VSSA RX_SYNTH SPI_DI SPI_CLK CLK_OUT RX_D5_N RX_D4_P RX_D3_P RX_D2_P RX_D1_P RX_D0_P VDDA1P3_ VDDA1P3_ P1_D8/ P1_D6/ P1_D4/ P1_D2/ P1_D0/ K RX1C_P VSSA RESETB SPI_ENB VSSD TX_SYNTH BB RX_D4_N RX_D3_N RX_D2_N RX_D1_N RX_D0_N L RX1C_N VSSA VSSA RBIAS AUXADC SPI_DO VSSA VSSA VSSA VSSA VSSA VSSA M RX1A_P RX1A_N NC VSSA TX_MON1 VSSA TX1A_P TX1A_N TX1B_P TX1B_N XTALP XTALN
002
ANALOG I/O DC POWER DIGITAL I/O GROUND
10453-
NO CONNECT
Figure 2. Pin Configuration, Top View
Table 13. Pin Function Descriptions Pin No. Type1 Mnemonic Description
A1, A2 I RX2A_N, RX2A_P Receive Channel 2 Differential Input A. Alternatively, each pin can be used as a single-ended input or combined to make a differential pair. Tie unused pins to ground. A3, M3 NC NC No Connect. Do not connect to these pins. A4, A6, B1, B2, I VSSA Analog Ground. Tie these pins directly to the VSSD digital ground on the printed B12, C2, C7 to circuit board (one ground plane). C12, F3, H2, H3, H6, J2, K2, L2, L3, L7 to L12, M4, M6 A5 I TX_MON2 Transmit Channel 2 Power Monitor Input. If this pin is unused, tie it to ground. A7, A8 O TX2A_N, TX2A_P Transmit Channel 2 Differential Output A. Tie unused pins to 1.3 V. A9, A10 O TX2B_N, TX2B_P Transmit Channel 2 Differential Output B. Tie unused pins to 1.3 V. A11 I VDDA1P1_TX_VCO Transmit VCO Supply Input. Connect to B11. A12 I TX_EXT_LO_IN External Transmit LO Input. If this pin is unused, tie it to ground. B3 O AUXDAC1 Auxiliary DAC 1 Output. B4 to B7 O GPO_3 to GPO_0 3.3 V Capable General-Purpose Outputs. B8 I VDD_GPO 2.5 V to 3.3 V Supply for the AUXDAC and General-Purpose Output Pins. When the VDD_GPO supply is not used, this supply must be set to 1.3 V. B9 I VDDA1P3_TX_LO Transmit LO 1.3 V Supply Input. B10 I VDDA1P3_TX_VCO_LDO Transmit VCO LDO 1.3 V Supply Input. Connect to B9. B11 O TX_VCO_LDO_OUT Transmit VCO LDO Output. Connect to A11 and a 1 µF bypass capacitor in series with a 1 Ω resistor to ground. C1, D1 I RX2C_P, RX2C_N Receive Channel 2 Differential Input C. Each pin can be used as a single-ended input or combined to make a differential pair. These inputs experience degraded performance above 3 GHz. Tie unused pins to ground. Rev. F | Page 16 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
AD9361 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 VDDA1P1_ TX_EXT_ A RX2A_N RX2A_P NC VSSA TX_MON2 VSSA TX2A_N TX2A_P TX2B_N TX2B_P TX_VCO LO_IN VDDA1P3_ VDDA1P3_ TX_VCO_ B VSSA VSSA AUXDAC1 GPO_3 GPO_2 GPO_1 GPO_0 VDD_GPO TX_VCO_ VSSA TX_LO LDO_OUT LDO TEST/ C RX2C_P VSSA AUXDAC2 ENABLE CTRL_IN0 CTRL_IN1 VSSA VSSA VSSA VSSA VSSA VSSA VDDA1P3_ VDDA1P3_ P0_D9/ P0_D7/ P0_D5/ P0_D3/ P0_D1/ RX2C_N CTRL_OUT0 CTRL_IN3 CTRL_IN2 VSSD D RX_RF RX_TX TX_D4_P TX_D3_P TX_D2_P TX_D1_P TX_D0_P VDDA1P3_ VDDA1P3_ P0_D11/ P0_D8/ P0_D6/ P0_D4/ P0_D2/ P0_D0/ E RX2B_P TX_LO_ CTRL_OUT1 CTRL_OUT2 CTRL_OUT3 RX_LO TX_D5_P TX_D4_N TX_D3_N TX_D2_N TX_D1_N TX_D0_N BUFFER VDDA1P3_ P0_D10/ VDDD1P3_ F RX2B_N RX_VCO_ VSSA CTRL_OUT6 CTRL_OUT5 CTRL_OUT4 VSSD TX_D5_N VSSD FB_CLK_P VSSD DIG LDO RX_EXT_ RX_VCO_ VDDA1P1_ RX_ RX_ TX_ DATA_ G CTRL_OUT7 EN_AGC ENABLE FB_CLK_N VSSD LO_IN LDO_OUT RX_VCO FRAME_N FRAME_P FRAME_P CLK_P P1_D11/ TX_ DATA_ VDD_ H RX1B_P VSSA VSSA TXNRX SYNC_IN VSSA VSSD VSSD RX_D5_P FRAME_N CLK_N INTERFACE VDDA1P3_ P1_D10/ P1_D9/ P1_D7/ P1_D5/ P1_D3/ P1_D1/ J RX1B_N VSSA RX_SYNTH SPI_DI SPI_CLK CLK_OUT RX_D5_N RX_D4_P RX_D3_P RX_D2_P RX_D1_P RX_D0_P VDDA1P3_ VDDA1P3_ P1_D8/ P1_D6/ P1_D4/ P1_D2/ P1_D0/ K RX1C_P VSSA RESETB SPI_ENB VSSD TX_SYNTH BB RX_D4_N RX_D3_N RX_D2_N RX_D1_N RX_D0_N L RX1C_N VSSA VSSA RBIAS AUXADC SPI_DO VSSA VSSA VSSA VSSA VSSA VSSA M RX1A_P RX1A_N NC VSSA TX_MON1 VSSA TX1A_P TX1A_N TX1B_P TX1B_N XTALP XTALN
002
ANALOG I/O DC POWER DIGITAL I/O GROUND
10453-
NO CONNECT
Figure 2. Pin Configuration, Top View
Table 13. Pin Function Descriptions Pin No. Type1 Mnemonic Description
A1, A2 I RX2A_N, RX2A_P Receive Channel 2 Differential Input A. Alternatively, each pin can be used as a single-ended input or combined to make a differential pair. Tie unused pins to ground. A3, M3 NC NC No Connect. Do not connect to these pins. A4, A6, B1, B2, I VSSA Analog Ground. Tie these pins directly to the VSSD digital ground on the printed B12, C2, C7 to circuit board (one ground plane). C12, F3, H2, H3, H6, J2, K2, L2, L3, L7 to L12, M4, M6 A5 I TX_MON2 Transmit Channel 2 Power Monitor Input. If this pin is unused, tie it to ground. A7, A8 O TX2A_N, TX2A_P Transmit Channel 2 Differential Output A. Tie unused pins to 1.3 V. A9, A10 O TX2B_N, TX2B_P Transmit Channel 2 Differential Output B. Tie unused pins to 1.3 V. A11 I VDDA1P1_TX_VCO Transmit VCO Supply Input. Connect to B11. A12 I TX_EXT_LO_IN External Transmit LO Input. If this pin is unused, tie it to ground. B3 O AUXDAC1 Auxiliary DAC 1 Output. B4 to B7 O GPO_3 to GPO_0 3.3 V Capable General-Purpose Outputs. B8 I VDD_GPO 2.5 V to 3.3 V Supply for the AUXDAC and General-Purpose Output Pins. When the VDD_GPO supply is not used, this supply must be set to 1.3 V. B9 I VDDA1P3_TX_LO Transmit LO 1.3 V Supply Input. B10 I VDDA1P3_TX_VCO_LDO Transmit VCO LDO 1.3 V Supply Input. Connect to B9. B11 O TX_VCO_LDO_OUT Transmit VCO LDO Output. Connect to A11 and a 1 µF bypass capacitor in series with a 1 Ω resistor to ground. C1, D1 I RX2C_P, RX2C_N Receive Channel 2 Differential Input C. Each pin can be used as a single-ended input or combined to make a differential pair. These inputs experience degraded performance above 3 GHz. Tie unused pins to ground. Rev. F | Page 16 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
