Datasheet ADN8833 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Ultracompact, 1 A Thermoelectric Cooler (TEC) Driver for Digital Control Systems |
| Pages / Page | 23 / 7 — Data Sheet. ADN8833. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. NDL. … |
| Revision | B |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
Data Sheet. ADN8833. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. NDL. TOP VIEW. (Not to Scale). DNC. DNC 1. 18 PGNDL. CONT 2. 17 LDR. PGNDL
Model Line for this Datasheet
Text Version of Document
link to page 7 link to page 7 link to page 7 link to page 9
Data Sheet ADN8833 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADN8833 NDL TOP VIEW G (Not to Scale) DNC DNC DNC DNC DNC P 1 2 3 4 5 24 23 22 21 20 19 DNC 1 18 PGNDL CONT 2 17 LDR A PGNDL PGNDL DNC DNC DNC VLIM/SD 3 ADN8833 16 PVINL TOP VIEW ILIM 4 15 PVINS (Not to Scale) VDD 5 14 SW VREF 6 13 PGNDS B VLIM/ LDR LDR DNC DNC SD 7 8 9 10 11 12 B C ND SY/ EC SF ITE NDS AG EN VT G P C PVIN PVIN ITEC CONT ILIM 2.54mm NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.
100
2. EXPOSED PAD. SOLDER TO THE ANALOG GROUND PLANE ON THE BOARD
12909-
D SW SW VTEC EN/SY VDD 0.5mm PITCH E PGNDS PGNDS SFB AGND VREF 2.54mm
002
NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.
12909- Figure 2. WLCSP Pin Configuration (Top View) Figure 3. LFCSP Pin Configuration (Top View)
Table 5. Pin Function Descriptions Pin No. WLCSP LFCSP Mnemonic Description
A1, A2 18, 19 PGNDL Power Ground of the Linear TEC Driver. A3 to 1, 20 to DNC Do Not Connect. Do not connect to these pins. A5, B3, 24 B4 B1, B2 17 LDR Output of the Linear TEC Driver. B5 3 VLIM/SD Voltage Limit/Shutdown. This pin sets the cooling and heating TEC voltage limits. When this pin is pulled low, the device shuts down. C1, C2 N/A1 PVIN Power Input for the TEC Driver. N/A1 16 PVINL Power input for the linear TEC driver N/A1 15 PVINS Power input for the PWM TEC driver C3 11 ITEC TEC Current Output. C4 2 CONT Control Input of the TEC Driver. Apply a control signal from the DAC to this pin to close the thermal loop. C5 4 ILIM Current Limit. This pin sets the TEC cooling and heating current limits. D1, D2 14 SW Switch Node Output of the PWM TEC Driver. D3 9 VTEC TEC Voltage Output. D4 8 EN/SY Enable/Synchronization. Set this pin high to enable the device. An external synchronization clock input can be applied to this pin. D5 5 VDD Power for the Driver Circuits. E1, E2 12, 13 PGNDS Power Ground of the PWM TEC Driver. E3 10 SFB Feedback of the PWM TEC Driver Output. E4 7 AGND Signal Ground. E5 6 VREF 2.5 V Reference Output. N/A1 0 EP Exposed Pad. Solder to the analog ground plane on the board. 1 N/A means not applicable. Rev. B | Page 7 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADN8833 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADN8833 NDL TOP VIEW G (Not to Scale) DNC DNC DNC DNC DNC P 1 2 3 4 5 24 23 22 21 20 19 DNC 1 18 PGNDL CONT 2 17 LDR A PGNDL PGNDL DNC DNC DNC VLIM/SD 3 ADN8833 16 PVINL TOP VIEW ILIM 4 15 PVINS (Not to Scale) VDD 5 14 SW VREF 6 13 PGNDS B VLIM/ LDR LDR DNC DNC SD 7 8 9 10 11 12 B C ND SY/ EC SF ITE NDS AG EN VT G P C PVIN PVIN ITEC CONT ILIM 2.54mm NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.
100
2. EXPOSED PAD. SOLDER TO THE ANALOG GROUND PLANE ON THE BOARD
12909-
D SW SW VTEC EN/SY VDD 0.5mm PITCH E PGNDS PGNDS SFB AGND VREF 2.54mm
002
NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.
12909- Figure 2. WLCSP Pin Configuration (Top View) Figure 3. LFCSP Pin Configuration (Top View)
Table 5. Pin Function Descriptions Pin No. WLCSP LFCSP Mnemonic Description
A1, A2 18, 19 PGNDL Power Ground of the Linear TEC Driver. A3 to 1, 20 to DNC Do Not Connect. Do not connect to these pins. A5, B3, 24 B4 B1, B2 17 LDR Output of the Linear TEC Driver. B5 3 VLIM/SD Voltage Limit/Shutdown. This pin sets the cooling and heating TEC voltage limits. When this pin is pulled low, the device shuts down. C1, C2 N/A1 PVIN Power Input for the TEC Driver. N/A1 16 PVINL Power input for the linear TEC driver N/A1 15 PVINS Power input for the PWM TEC driver C3 11 ITEC TEC Current Output. C4 2 CONT Control Input of the TEC Driver. Apply a control signal from the DAC to this pin to close the thermal loop. C5 4 ILIM Current Limit. This pin sets the TEC cooling and heating current limits. D1, D2 14 SW Switch Node Output of the PWM TEC Driver. D3 9 VTEC TEC Voltage Output. D4 8 EN/SY Enable/Synchronization. Set this pin high to enable the device. An external synchronization clock input can be applied to this pin. D5 5 VDD Power for the Driver Circuits. E1, E2 12, 13 PGNDS Power Ground of the PWM TEC Driver. E3 10 SFB Feedback of the PWM TEC Driver Output. E4 7 AGND Signal Ground. E5 6 VREF 2.5 V Reference Output. N/A1 0 EP Exposed Pad. Solder to the analog ground plane on the board. 1 N/A means not applicable. Rev. B | Page 7 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE
