Datasheet AD8611, AD8612 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Ultrafast, 4 ns Single-Supply Comparators |
| Pages / Page | 20 / 6 — AD8611/AD8612. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. … |
| Revision | B |
| File Format / Size | PDF / 317 Kb |
| Document Language | English |
AD8611/AD8612. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. V+ 1. IN+ 2. AD8611. IN– 3. TOP VIEW. GND. (Not to Scale). LATCH
Model Line for this Datasheet
Text Version of Document
AD8611/AD8612 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V+ 1 8 QA IN+ 2 AD8611 7 QA IN– 3 6 TOP VIEW GND
001
V– (Not to Scale) 4 5 LATCH
06010- Figure 4. 8-Lead Narrow Body SOIC Pin Configuration
V+ 1 8 QA IN+ AD8611 2 7 QA TOP VIEW IN– 3 6 GND (Not to Scale)
002
V– 4 5 LATCH
06010- Figure 5. 8-Lead MSOP Pin Configuration
QA 1 14 QB QA 2 13 QB GND 3 AD8612 12 GND TOP VIEW LEA 4 11 LEB (Not to Scale) V– 5 10 V+ INA– 6 9 INB–
003
INA+ 7 8 INB+
06010- Figure 6. 14-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions Pin No. SOIC and MSOP TSSOP Mnemonic Description
1 10 V+ Positive Supply Terminal. 2 IN+ Noninverting Analog Input of the Differential Input Stage. 3 IN− Inverting Analog Input of the Differential Input Stage. 4 5 V− Negative Supply Terminal. 5 LATCH Latch Enable Input. 6 3, 12 GND Negative Logic Supply 7 1 QA One of Two Complementary Output for Channel A. 8 2 QA One of Two Complementary Output for Channel A. 14 QB One of Two Complementary Output for Channel B. 13 QB One of Two Complementary Output for Channel B. 4 LEA Channel A Latch Enable. 11 LEB Channel B Latch Enable. 7 INA+ Noninverting Analog Input of the Differential Input Stage for Channel A. 6 INA− Inverting Analog Input of the Differential Input Stage for Channel A. 8 INB+ Noninverting Analog Input of the Differential Input Stage for Channel B. 9 INB− Inverting Analog Input of the Differential Input Stage for Channel B. Rev. B | Page 6 of 20 Document Outline FEATURES APPLICATIONS PIN CONFIGURATIONS GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION OPTIMIZING HIGH SPEED PERFORMANCE UPGRADING THE LT1394 AND LT1016 MAXIMUM INPUT FREQUENCY AND OVERDRIVE OUTPUT LOADING CONSIDERATIONS USING THE LATCHTO MAINTAIN A CONSTANT OUTPUT INPUT STAGE AND BIAS CURRENTS USING HYSTERESIS CLOCK TIMING RECOVERY A 5 V, HIGH SPEED WINDOW COMPARATOR OUTLINE DIMENSIONS ORDERING GUIDE
001
V– (Not to Scale) 4 5 LATCH
06010- Figure 4. 8-Lead Narrow Body SOIC Pin Configuration
V+ 1 8 QA IN+ AD8611 2 7 QA TOP VIEW IN– 3 6 GND (Not to Scale)
002
V– 4 5 LATCH
06010- Figure 5. 8-Lead MSOP Pin Configuration
QA 1 14 QB QA 2 13 QB GND 3 AD8612 12 GND TOP VIEW LEA 4 11 LEB (Not to Scale) V– 5 10 V+ INA– 6 9 INB–
003
INA+ 7 8 INB+
06010- Figure 6. 14-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions Pin No. SOIC and MSOP TSSOP Mnemonic Description
1 10 V+ Positive Supply Terminal. 2 IN+ Noninverting Analog Input of the Differential Input Stage. 3 IN− Inverting Analog Input of the Differential Input Stage. 4 5 V− Negative Supply Terminal. 5 LATCH Latch Enable Input. 6 3, 12 GND Negative Logic Supply 7 1 QA One of Two Complementary Output for Channel A. 8 2 QA One of Two Complementary Output for Channel A. 14 QB One of Two Complementary Output for Channel B. 13 QB One of Two Complementary Output for Channel B. 4 LEA Channel A Latch Enable. 11 LEB Channel B Latch Enable. 7 INA+ Noninverting Analog Input of the Differential Input Stage for Channel A. 6 INA− Inverting Analog Input of the Differential Input Stage for Channel A. 8 INB+ Noninverting Analog Input of the Differential Input Stage for Channel B. 9 INB− Inverting Analog Input of the Differential Input Stage for Channel B. Rev. B | Page 6 of 20 Document Outline FEATURES APPLICATIONS PIN CONFIGURATIONS GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION OPTIMIZING HIGH SPEED PERFORMANCE UPGRADING THE LT1394 AND LT1016 MAXIMUM INPUT FREQUENCY AND OVERDRIVE OUTPUT LOADING CONSIDERATIONS USING THE LATCHTO MAINTAIN A CONSTANT OUTPUT INPUT STAGE AND BIAS CURRENTS USING HYSTERESIS CLOCK TIMING RECOVERY A 5 V, HIGH SPEED WINDOW COMPARATOR OUTLINE DIMENSIONS ORDERING GUIDE
