Datasheet EFM8LB1 (Silicon Labs) - 9
| Manufacturer | Silicon Labs |
| Description | EFM8 Laser Bee Family |
| Pages / Page | 77 / 9 — 3.2 Power. Table 3.1. Power Modes. Power Mode. Details. Mode Entry. … |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
3.2 Power. Table 3.1. Power Modes. Power Mode. Details. Mode Entry. Wake-Up Sources. 3.3 I/O. silabs.com
Model Line for this Datasheet
- EFM8LB10F16E-C-QFN24 EFM8LB10F16E-C-QFN32 EFM8LB10F16E-C-QFP32 EFM8LB10F16E-C-QSOP24 EFM8LB10F16ES0-C-QFN24 EFM8LB10F16ES0-C-QFN32 EFM8LB10F16ES1-C-QFN24 EFM8LB10F16ES1-C-QFN32 EFM8LB11F16E-C-QFN24 EFM8LB11F16E-C-QFN32 EFM8LB11F16E-C-QFP32 EFM8LB11F16E-C-QSOP24 EFM8LB11F16ES0-C-QFN24 EFM8LB11F16ES0-C-QFN32 EFM8LB11F16ES1-C-QFN24 EFM8LB11F16ES1-C-QFN32 EFM8LB11F32E-C-QFN24 EFM8LB11F32E-C-QFN32 EFM8LB11F32E-C-QFP32 EFM8LB11F32E-C-QSOP24 EFM8LB11F32ES0-C-QFN24 EFM8LB11F32ES0-C-QFN32 EFM8LB11F32ES1-C-QFN24 EFM8LB11F32ES1-C-QFN32 EFM8LB12F32E-C-QFN24 EFM8LB12F32E-C-QFN32 EFM8LB12F32E-C-QFP32 EFM8LB12F32E-C-QSOP24 EFM8LB12F32ES0-C-QFN24 EFM8LB12F32ES0-C-QFN32 EFM8LB12F32ES1-C-QFN24 EFM8LB12F32ES1-C-QFN32 EFM8LB12F64E-C-QFN24 EFM8LB12F64E-C-QFN32 EFM8LB12F64E-C-QFP32 EFM8LB12F64E-C-QSOP24 EFM8LB12F64ES0-C-QFN24 EFM8LB12F64ES0-C-QFN32 EFM8LB12F64ES1-C-QFN24 EFM8LB12F64ES1-C-QFN32
Text Version of Document
EFM8LB1 Data Sheet System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi- ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little power when they are not in use.
Table 3.1. Power Modes Power Mode Details Mode Entry Wake-Up Sources
Normal Core and all peripherals clocked and fully operational Idle • Core halted Set IDLE bit in PCON0 Any interrupt • All peripherals clocked and fully operational • Code resumes execution on wake event Suspend • Core and peripheral clocks halted 1. Switch SYSCLK to • Timer 4 Event • HFOSC0 and HFOSC1 oscillators stopped HFOSC0 • SPI0 Activity • Regulator in normal bias mode for fast wake 2. Set SUSPEND bit in • I2C0 Slave Activity PCON1 • Timer 3 and 4 may clock from LFOSC0 • Port Match Event • Code resumes execution on wake event • Comparator 0 Falling Edge • CLUn Interrupt-Enabled Event Stop • All internal power nets shut down 1. Clear STOPCF bit in Any reset source • Pins retain state REG0CN • Exit on any reset source 2. Set STOP bit in PCON0 Snooze • Core and peripheral clocks halted 1. Switch SYSCLK to • Timer 4 Event • HFOSC0 and HFOSC1 oscillators stopped HFOSC0 • SPI0 Activity • Regulator in low bias current mode for energy sav- 2. Set SNOOZE bit in • I2C0 Slave Activity ings PCON1 • Port Match Event • Timer 3 and 4 may clock from LFOSC0 • Comparator 0 Falling • Code resumes execution on wake event Edge • CLUn Interrupt-Enabled Event Shutdown • All internal power nets shut down 1. Set STOPCF bit in • RSTb pin reset • Pins retain state REG0CN • Power-on reset • Exit on pin or power-on reset 2. Set STOP bit in PCON0
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P2.3 can be defined as gen- eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an analog function. Port pins P2.4 to P3.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P3.0 or P3.7, depending on the package option. The port control block offers the following features: • Up to 29 multi-functions I/O pins, supporting digital and analog functions. • Flexible priority crossbar decoder for digital peripheral assignment. • Two drive strength settings for each port. • State retention feature allows pins to retain configuration through most reset sources. • Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1). • Up to 24 direct-pin interrupt sources with shared interrupt vector (Port Match).
silabs.com
| Building a more connected world. Rev. 1.3 | 9 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Power 3.3 I/O 3.4 Clocking 3.5 Counters/Timers and PWM 3.6 Communications and Other Digital Peripherals 3.7 Analog 3.8 Reset Sources 3.9 Debugging 3.10 Bootloader 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Recommended Operating Conditions 4.1.2 Power Consumption 4.1.3 Reset and Supply Monitor 4.1.4 Flash Memory 4.1.5 Power Management Timing 4.1.6 Internal Oscillators 4.1.7 External Clock Input 4.1.8 External Oscillator 4.1.9 ADC 4.1.10 Voltage Reference 4.1.11 Temperature Sensor 4.1.12 1.8 V Internal LDO Voltage Regulator 4.1.13 DACs 4.1.14 Comparators 4.1.15 Configurable Logic 4.1.16 Port I/O 4.1.17 SMBus 4.2 Thermal Conditions 4.3 Absolute Maximum Ratings 5. Typical Connection Diagrams 5.1 Power 5.2 Debug 5.3 Other Connections 6. Pin Definitions 6.1 EFM8LB1x-QFN32 Pin Definitions 6.2 EFM8LB1x-QFP32 Pin Definitions 6.3 EFM8LB1x-QFN24 Pin Definitions 6.4 EFM8LB1x-QSOP24 Pin Definitions 7. QFN32 Package Specifications 7.1 Package Dimensions 7.2 PCB Land Pattern 7.3 Package Marking 8. QFP32 Package Specifications 8.1 Package Dimensions 8.2 PCB Land Pattern 8.3 Package Marking 9. QFN24 Package Specifications 9.1 Package Dimensions 9.2 PCB Land Pattern 9.3 Package Marking 10. QSOP24 Package Specifications 10.1 Package Dimensions 10.2 PCB Land Pattern 10.3 Package Marking 11. Revision History
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi- ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little power when they are not in use.
Table 3.1. Power Modes Power Mode Details Mode Entry Wake-Up Sources
Normal Core and all peripherals clocked and fully operational Idle • Core halted Set IDLE bit in PCON0 Any interrupt • All peripherals clocked and fully operational • Code resumes execution on wake event Suspend • Core and peripheral clocks halted 1. Switch SYSCLK to • Timer 4 Event • HFOSC0 and HFOSC1 oscillators stopped HFOSC0 • SPI0 Activity • Regulator in normal bias mode for fast wake 2. Set SUSPEND bit in • I2C0 Slave Activity PCON1 • Timer 3 and 4 may clock from LFOSC0 • Port Match Event • Code resumes execution on wake event • Comparator 0 Falling Edge • CLUn Interrupt-Enabled Event Stop • All internal power nets shut down 1. Clear STOPCF bit in Any reset source • Pins retain state REG0CN • Exit on any reset source 2. Set STOP bit in PCON0 Snooze • Core and peripheral clocks halted 1. Switch SYSCLK to • Timer 4 Event • HFOSC0 and HFOSC1 oscillators stopped HFOSC0 • SPI0 Activity • Regulator in low bias current mode for energy sav- 2. Set SNOOZE bit in • I2C0 Slave Activity ings PCON1 • Port Match Event • Timer 3 and 4 may clock from LFOSC0 • Comparator 0 Falling • Code resumes execution on wake event Edge • CLUn Interrupt-Enabled Event Shutdown • All internal power nets shut down 1. Set STOPCF bit in • RSTb pin reset • Pins retain state REG0CN • Power-on reset • Exit on pin or power-on reset 2. Set STOP bit in PCON0
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P2.3 can be defined as gen- eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an analog function. Port pins P2.4 to P3.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P3.0 or P3.7, depending on the package option. The port control block offers the following features: • Up to 29 multi-functions I/O pins, supporting digital and analog functions. • Flexible priority crossbar decoder for digital peripheral assignment. • Two drive strength settings for each port. • State retention feature allows pins to retain configuration through most reset sources. • Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1). • Up to 24 direct-pin interrupt sources with shared interrupt vector (Port Match).
silabs.com
| Building a more connected world. Rev. 1.3 | 9 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Power 3.3 I/O 3.4 Clocking 3.5 Counters/Timers and PWM 3.6 Communications and Other Digital Peripherals 3.7 Analog 3.8 Reset Sources 3.9 Debugging 3.10 Bootloader 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Recommended Operating Conditions 4.1.2 Power Consumption 4.1.3 Reset and Supply Monitor 4.1.4 Flash Memory 4.1.5 Power Management Timing 4.1.6 Internal Oscillators 4.1.7 External Clock Input 4.1.8 External Oscillator 4.1.9 ADC 4.1.10 Voltage Reference 4.1.11 Temperature Sensor 4.1.12 1.8 V Internal LDO Voltage Regulator 4.1.13 DACs 4.1.14 Comparators 4.1.15 Configurable Logic 4.1.16 Port I/O 4.1.17 SMBus 4.2 Thermal Conditions 4.3 Absolute Maximum Ratings 5. Typical Connection Diagrams 5.1 Power 5.2 Debug 5.3 Other Connections 6. Pin Definitions 6.1 EFM8LB1x-QFN32 Pin Definitions 6.2 EFM8LB1x-QFP32 Pin Definitions 6.3 EFM8LB1x-QFN24 Pin Definitions 6.4 EFM8LB1x-QSOP24 Pin Definitions 7. QFN32 Package Specifications 7.1 Package Dimensions 7.2 PCB Land Pattern 7.3 Package Marking 8. QFP32 Package Specifications 8.1 Package Dimensions 8.2 PCB Land Pattern 8.3 Package Marking 9. QFN24 Package Specifications 9.1 Package Dimensions 9.2 PCB Land Pattern 9.3 Package Marking 10. QSOP24 Package Specifications 10.1 Package Dimensions 10.2 PCB Land Pattern 10.3 Package Marking 11. Revision History
