Datasheet ADSP-21065L (Analog Devices) - 2

ADSP-21065L 544 Kbits Configurable On-Chip SRAM Host Processor Interface Dual-Ported for Independent Access by Core Processor Efficient Interface to 8-, 16-, and 32-Bit Microprocessors and DMA Host Can Directly Read/Write ADSP-21065L IOP Registers Configurable in Combinations of 16-, 32-, 48-Bit Data and Multiprocessing Program Words in Block 0 and Block 1 Distributed On-Chip Bus Arbitration for Glueless, Parallel DMA Controller Bus Connect Between Two ADSP-21065Ls Plus Host Ten DMA Channels—Two Dedicated to the External Port 132 Mbytes/s Transfer Rate Over Parallel Bus and Eight Dedicated to the Serial Ports Serial Ports Background DMA Transfers at up to 66 MHz, in Parallel Independent Transmit and Receive Functions with Full Speed Processor Execution Programmable 3-Bit to 32-Bit Serial Word Width Performs Transfers Between: I2S Support Allowing Eight Transmit and Eight Receive Internal RAM and Host Channels Internal RAM and Serial Ports Glueless Interface to Industry Standard Codecs Internal RAM and Master or Slave SHARC TDM Multichannel Mode with
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-Law/A-Law Hardware Internal RAM and External Memory or I/O Devices Companding External Memory and External Devices Multichannel Signaling Protocol
–2– REV. C Document Outline SUMMARY KEY FEATURES Flexible Data Formats and 40-Bit Extended Precision Parallel Computations 544 Kbits Configurable On-Chip SRAM DMA Controller Host Processor Interface Multiprocessing Serial Ports GENERAL DESCRIPTION ADSP-21000 FAMILY CORE ARCHITECTURE Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Two Operands Instruction Cache Data Address Generators with Hardware Circular Buffers Flexible Instruction Set ADSP-21065L FEATURES Dual-Ported On-Chip Memory Off-Chip Memory and Peripherals Interface SDRAM Interface Host Processor Interface DMA Controller Serial Ports Programmable Timers and General-Purpose I/O Ports Program Booting Multiprocessing DEVELOPMENT TOOLS Additional Information PIN DESCRIPTIONS CLOCK SIGNALS TARGET BOARD CONNECTOR FOR EZ-ICE PROBE SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION ADSP-21065L TIMING SPECIFICATIONS General Notes Memory Read—Bus Master Memory Write—Bus Master Synchronous Read/Write—Bus Master Synchronous Read/Write—Bus Slave Multiprocessor Bus Request and Host Bus Request Asynchronous Read/Write—Host to ADSP-21065L Three-State Timing—Bus Master, Bus Slave, HBR, SBTS DMA Handshake SDRAM Interface—Bus Master SDRAM Interface—Bus Slave Serial Ports JTAG Test Access Port and Emulation OUTPUT DRIVE CURRENT TEST CONDITIONS Output Disable Time Example System Hold Time Calculation Capacitive Loading POWER DISSIPATION ENVIRONMENTAL CONDITIONS Thermal Characteristics 208-LEAD MQFP PIN CONFIGURATION 208-LEAD MQFP PIN OUTLINE DIMENSIONS 208-Lead Plastic Quad Flatpack Package [MQFP] 196-BALL MINI-BGA PIN CONFIGURATION 196-BALL MINI-BGA PIN CONFIGURATION ORDERING GUIDE OUTLINE DIMENSIONS 196-Lead Chip Scale Ball Grid Array [CSPBGA] Revision History