Datasheet ADSP-21065L (Analog Devices) - 3

ADSP-21065L GENERAL DESCRIPTION ADSP-21065L
The ADSP-21065L is a powerful member of the SHARC
#1 CS
family of 32-bit processors optimized for cost sensitive appli-
CLOCK CLKIN BOOT ADDR EPROM
cations. The SHARC—Super Harvard Architecture—offers the
RESET RESET (OPTIONAL) DATA
highest levels of performance and memory integration of any
CONTROL ADDRESS DATA
32-bit DSP in the industry—they are also the only DSP in the
01 ID1-0 ADDR23-0 HOST
industry that offer both fixed and floating-point capabilities,
DATA PROCESSOR 31-0 SPORT0 (OPTIONAL)
without compromising precision or performance.
TX0_A RD CS
The ADSP-21065L is fabricated in a high speed, low power
TX0_B WR ADDR RX0_A ACK
CMOS process, 0.35 mm technology. With its on-chip instruc-
DATA RX0_B MS3-0
tion cache, the processor can execute every instruction in a
BMS
single cycle. Table I lists the performance benchmarks for the
SPORT1 ADDR SBTS
ADSP-21065L.
TX1_A SW DATA TX1_B CS
The ADSP-21065L SHARC combines a floating-point DSP
RX1_A HBR RX1_B HBG CS SDRAM
core with integrated, on-chip system features, including a
(OPTIONAL) REDY
544 Kbit SRAM memory, host processor interface, DMA con-
CONTROL RAS RAS
troller, SDRAM controller, and enhanced serial ports.
CAS CAS DQM DQM
Figure 1 shows a block diagram of the ADSP-21065L, illustrat-
SDWE WE
ing the following architectural features:
SDCLK CLK 1-0 SDCKE CKE
Computation Units (ALU, Multiplier, and Shifter) with a
A10 SDA10
Shared Data Register File
CPA
Data Address Generators (DAG1, DAG2)
BR2
Program Sequencer with Instruction Cache
BR1
Timers with Event Capture Modes On-Chip, dual-ported SRAM Figure 2. ADSP-21065L Single-Processor System External Port for Interfacing to Off-Chip Memory and
Independent, Parallel Computation Units
Peripherals The arithmetic/logic unit (ALU), multiplier, and shifter all Host Port and SDRAM Interface perform single-cycle instructions. The three units are arranged DMA Controller in parallel, maximizing computational throughput. Single multi- Enhanced Serial Ports function instructions execute parallel ALU and multiplier JTAG Test Access Port operations. These computation units support IEEE 32-bit single-precision floating-point, extended precision 40-bit floating-
Table I. Performance Benchmarks
point, and 32-bit fixed-point data formats.
Benchmark Timing Cycles Data Register File
A general-purpose data register file is used for transferring data Cycle Time 15.00 ns 1 between the computation units and the data buses, and for 1024-Pt. Complex FFT storing intermediate results. This 10-port, 32-register (16 primary, (Radix 4, with Digit Reverse) 0.274 ns 18221 16 secondary) register file, combined with the ADSP-21000 Matrix Multiply (Pipelined) Harvard architecture, allows unconstrained data flow between [3 ¥ 3] ¥ [3 ¥ 1] 135 ns 9 computation units and internal memory. [4 ¥ 4] ¥ [4 ¥ 1] 240 ns 16
Single-Cycle Fetch of Instruction and Two Operands
FIR Filter (per Tap) 15 ns 1 The ADSP-21065L features an enhanced Super Harvard Archi- IIR Filter (per Biquad) 60 ns 4 tecture in which the data memory (DM) bus transfers data and Divide Y/X 90 ns 6 the program memory (PM) bus transfers both instructions and data (see Figure 1). With its separate program and data memory Inverse Square Root (1/÷x) 135 ns 9 buses, and on-chip instruction cache, the processor can simulta- DMA Transfers 264 Mbytes/sec. neously fetch two operands and an instruction (from the cache), all in a single cycle.
ADSP-21000 FAMILY CORE ARCHITECTURE Instruction Cache
The ADSP-21065L is code and function compatible with the The ADSP-21065L includes an on-chip instruction cache that ADSP-21060/ADSP-21061/ADSP-21062. The ADSP-21065L enables three-bus operation for fetching an instruction and two includes the following architectural features of the SHARC data values. The cache is selective—only the instructions that family core. fetches conflict with PM bus data accesses are cached. This allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The ADSP-21065L’s two data address generators (DAGs) implement circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data REV. C –3– Document Outline SUMMARY KEY FEATURES Flexible Data Formats and 40-Bit Extended Precision Parallel Computations 544 Kbits Configurable On-Chip SRAM DMA Controller Host Processor Interface Multiprocessing Serial Ports GENERAL DESCRIPTION ADSP-21000 FAMILY CORE ARCHITECTURE Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Two Operands Instruction Cache Data Address Generators with Hardware Circular Buffers Flexible Instruction Set ADSP-21065L FEATURES Dual-Ported On-Chip Memory Off-Chip Memory and Peripherals Interface SDRAM Interface Host Processor Interface DMA Controller Serial Ports Programmable Timers and General-Purpose I/O Ports Program Booting Multiprocessing DEVELOPMENT TOOLS Additional Information PIN DESCRIPTIONS CLOCK SIGNALS TARGET BOARD CONNECTOR FOR EZ-ICE PROBE SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION ADSP-21065L TIMING SPECIFICATIONS General Notes Memory Read—Bus Master Memory Write—Bus Master Synchronous Read/Write—Bus Master Synchronous Read/Write—Bus Slave Multiprocessor Bus Request and Host Bus Request Asynchronous Read/Write—Host to ADSP-21065L Three-State Timing—Bus Master, Bus Slave, HBR, SBTS DMA Handshake SDRAM Interface—Bus Master SDRAM Interface—Bus Slave Serial Ports JTAG Test Access Port and Emulation OUTPUT DRIVE CURRENT TEST CONDITIONS Output Disable Time Example System Hold Time Calculation Capacitive Loading POWER DISSIPATION ENVIRONMENTAL CONDITIONS Thermal Characteristics 208-LEAD MQFP PIN CONFIGURATION 208-LEAD MQFP PIN OUTLINE DIMENSIONS 208-Lead Plastic Quad Flatpack Package [MQFP] 196-BALL MINI-BGA PIN CONFIGURATION 196-BALL MINI-BGA PIN CONFIGURATION ORDERING GUIDE OUTLINE DIMENSIONS 196-Lead Chip Scale Ball Grid Array [CSPBGA] Revision History