Datasheet ADSP-21065L (Analog Devices) - 10

ADSP-21065L Pin Type Function
SDA10 O/T
SDRAM A10 Pin.
Enables applications to refresh an SDRAM in parallel with a host access. XTAL O
Crystal Oscillator Terminal.
Used in conjunction with CLKIN to enable the ADSP-21065L’s internal clock generator or to disable it to use an external clock source. See CLKIN. PWM_EVENT1-0 I/O/A
PWM Output/Event Capture.
In PWMOUT mode, is an output pin and functions as a timer counter. In WIDTH_CNT mode, is an input pin and functions as a pulse counter/event capture. VDD P
Power Supply;
nominally +3.3 V dc. (33 pins) GND G
Power Supply Return
. (37 pins) NC
Do Not Connect.
Reserved pins that must be left open and unconnected. (7 pins)
CLOCK SIGNALS TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-21065L can use an external clock or a crystal. See The ADSP-2106x EZ-ICE emulator uses the IEEE 1149.1 CLKIN pin description. You can configure the ADSP-21065L JTAG test access port of the ADSP-2106x to monitor and con- to use its internal clock generator by connecting the necessary trol the target board processor during emulation. The EZ-ICE components to CLKIN and XTAL. You can use either a crystal probe requires the ADSP-2106x’s CLKIN, TMS, TCK, TRST, operating in the fundamental mode or a crystal operating at an TDI, TDO, EMU and GND signals be made accessible on the overtone. Figure 4 shows the component connections used for a target system via a 14-pin connector (a 2 row x 7 pin strip header) crystal operating in fundamental mode, and Figure 5 shows such as that shown in Figure 6. The EZ-ICE probe plugs directly the component connections used for a crystal operating at an onto this connector for chip-on-board emulation. You must add overtone. this connector to your target board design if you, intend to use the ADSP-2106x EZ-ICE.
CLKIN XTAL
The total trace length between the EZ-ICE connector and the furthest device sharing the EZ-ICE JTAG pins should be lim-
X1
ited to 15 inches maximum for guaranteed operation. This
C1 C2
restriction on length must include EZ-ICE JTAG signals, which are routed to one or more 2106x devices or to a combination of 2106xs and other JTAG devices on the chain.
SUGGESTED COMPONENTS FOR 30 MHz OPERATION:
The 14-pin, 2-row pin strip header is keyed at the Pin 3 loca-
ECLIPTEK EC2SM-33-30.000M (SURFACE MOUNT PACKAGE) ECLIPTEK EC-33-30.000M (THROUGH-HOLE PACKAGE)
tion—you must remove Pin 3 from the header. The pins must
C1 = 33pF
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
C2 = 27pF NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
ing should be 0.1 ¥ 0.1 inches. Pin strip headers are available
CONTACT CRYSTAL MANUFACTURER FOR DETAILS.
from vendors such as 3M, McKenzie and Samtec. Figure 4. 30 MHz Operation (Fundamental Mode Crystal)
1 2 CLKIN XTAL GND EMU RS 3 4 X1 KEY (NO PIN) CLKIN (OPTIONAL) C3 C1 C2 5 6 L1 BTMS TMS 7 8 SUGGESTED COMPONENTS FOR 30MHz OPERATION: BTCK TCK ECLIPTEK EC2SM-T-30.000M (SURFACE MOUNT PACKAGE) ECLIPTEK ECT-30.000M (THROUGH-HOLE PACKAGE) 9 10 C1 = 18pF BTRST 9 TRST C2 = 27pF C3 = 75pF 11 12 L1 = 3300nH RS = SEE NOTE. BTDI TDI NOTE: C1, C2, C3, RS AND L1 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT MANUFACTURER FOR DETAILS. 13 14 GND TDO
Figure 5. 30 MHz Operation (3rd Overtone Crystal)
TOP VIEW
Figure 6. Target Board Connector for ADSP-2106x EZ-ICE (JTAG Header) –10– REV. C Document Outline SUMMARY KEY FEATURES Flexible Data Formats and 40-Bit Extended Precision Parallel Computations 544 Kbits Configurable On-Chip SRAM DMA Controller Host Processor Interface Multiprocessing Serial Ports GENERAL DESCRIPTION ADSP-21000 FAMILY CORE ARCHITECTURE Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Two Operands Instruction Cache Data Address Generators with Hardware Circular Buffers Flexible Instruction Set ADSP-21065L FEATURES Dual-Ported On-Chip Memory Off-Chip Memory and Peripherals Interface SDRAM Interface Host Processor Interface DMA Controller Serial Ports Programmable Timers and General-Purpose I/O Ports Program Booting Multiprocessing DEVELOPMENT TOOLS Additional Information PIN DESCRIPTIONS CLOCK SIGNALS TARGET BOARD CONNECTOR FOR EZ-ICE PROBE SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION ADSP-21065L TIMING SPECIFICATIONS General Notes Memory Read—Bus Master Memory Write—Bus Master Synchronous Read/Write—Bus Master Synchronous Read/Write—Bus Slave Multiprocessor Bus Request and Host Bus Request Asynchronous Read/Write—Host to ADSP-21065L Three-State Timing—Bus Master, Bus Slave, HBR, SBTS DMA Handshake SDRAM Interface—Bus Master SDRAM Interface—Bus Slave Serial Ports JTAG Test Access Port and Emulation OUTPUT DRIVE CURRENT TEST CONDITIONS Output Disable Time Example System Hold Time Calculation Capacitive Loading POWER DISSIPATION ENVIRONMENTAL CONDITIONS Thermal Characteristics 208-LEAD MQFP PIN CONFIGURATION 208-LEAD MQFP PIN OUTLINE DIMENSIONS 208-Lead Plastic Quad Flatpack Package [MQFP] 196-BALL MINI-BGA PIN CONFIGURATION 196-BALL MINI-BGA PIN CONFIGURATION ORDERING GUIDE OUTLINE DIMENSIONS 196-Lead Chip Scale Ball Grid Array [CSPBGA] Revision History