link to page 4 link to page 6 link to page 6 link to page 4 link to page 4 link to page 5 link to page 6 link to page 6 link to page 4 link to page 4 ADL8111Data SheetPIN CONFIGURATION AND FUNCTION DESCRIPTIONS_ANDUTNDNDNDNDGOGGGIN_AG282726252423 22VDD_PA121GNDVBIAS2ADL811120GNDGND319GNDGNDGNDRFIN418RFOUTGNDTOP VIEW517GND(Not to Scale)VA616VDD_SWGNDGNDVB715VSS_SW891011121314ND_BNDNDNDNDGUTGGGIN_BGONOTES 005 1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND. 20106- Figure 5. Pin Configuration—Top View Not to Scale Table 7. Pin Function Descriptions Pin No.MnemonicDescription 1 VDD_PA Drain Bias Voltage. See Table 2. 2 VBIAS Current Mirror Bias Resistor Pin. Use this pin to set the current to the internal resistor by the external resistor. See Figure 9 for the interface schematic. 3, 5, 8, 10 to 12, 14, 17, 19 to GND RF and DC Ground. See Figure 6 for the interface schematic. 22, 24 to 26, 28 4 RFIN RF Input. These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. 6, 7 VA, VB Control Input. See Table 2, Table 4, and Table 5. See Figure 8 and Figure 7 for the interface schematics. 9, 13 OUT_B, These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF IN_B line potential is not equal to 0 V dc. 15 VSS_SW Negative Bias Voltage. See Table 2. 16 VDD_SW Positive Bias Voltage. See Table 2. 18 RFOUT RF Output. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. 23, 27 IN_A, These pins are dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF OUT_A line potential is not equal to 0 V dc. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground. INTERFACE SCHEMATICSVDD_SWGNDVA 008 006 20106- 20106- Figure 6. GND Interface Schematic Figure 8. VA Interface Schematic VBIASVDD_SWVB 007 20106- 109 20106- Figure 7. VB Interface Schematic Figure 9. VBIAS Interface Schematic Rev. 0 | Page 6 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE POWER DERATING CURVES ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL BYPASS A STATE INTERNAL AMPLIFIER STATE INTERNAL BYPASS STATE EXTERNAL BYPASS B STATE TEST CIRCUITS THEORY OF OPERATION SIGNAL PATH STATES FOR DIGITAL CONTROL INPUTS APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING During Power-Up During Power-Down EVALUATION PCB EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE