link to page 19 link to page 19 link to page 19 link to page 19 link to page 19 link to page 19 Data SheetADL8111TYPICAL PERFORMANCE CHARACTERISTICSEXTERNAL BYPASS A STATE0B)0B)d–1d((S–2S–2SS–3OO–4–4–5RFIN TO OUT_A INPUT RETURN LOSSURN L–6RFIN TO OUT_A INSERTION LOSSURN LT–6RFIN TO OUT_A OUTPUT RETURN LOSST–7 –8–8–9+85°C–10+25°CN AND RE–10N AND RE–11–40°CIOIO–12RT–12RTE–13ENS–14NS–14–15 –16–16–17ADBAND I–18ADBAND I–18–19BRO–20BRO–20012345678910 010 012345678 013 FREQUENCY (GHz) 20106- FREQUENCY (GHz) 20106- Figure 10. Broadband Insertion and Return Loss vs. Frequency, Figure 13. Broadband Insertion and Return Loss vs. Frequency, State = External Bypass A, Path = RFIN to OUT_A (Refer to Figure 75 for the State = External Bypass A, Path = IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) Test Circuit) 00–1–1–2–2))–3–3dBdB((S–4S–4LOS–5LOS–5TION+85°C+85°C–6TIONR+25°C–6R+25°CEES–40°CS–40°C–7IN–7IN–8–8–9–9–10 1 –10 1 012345678 0 012345678 014 FREQUENCY (GHz) 20106- FREQUENCY (GHz) 20106- Figure 11. Insertion Loss Over Temperature vs. Frequency, Figure 14. Insertion Loss Over Temperature vs. Frequency, State = External Bypass A, Path = RFIN to OUT_A (Refer to Figure 75 for the State = External Bypass A, Path = IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) Test Circuit) 00+85°C+85°C–5+25°C–5+25°C–40°C–40°CB)B)dd((SSSSO–10O–10URN LURN LTT–15–15REREUTUTINPINP–20–20–25–25012345678 012 012345678 015 FREQUENCY (GHz) 20106- FREQUENCY (GHz) 20106- Figure 12. Input Return Loss Over Temperature vs. Frequency, Figure 15. Input Return Loss Over Temperature vs. Frequency, State = External Bypass A, Path = RFIN to OUT_A (Refer to Figure 75 for the State = External Bypass A, Path = IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) Test Circuit) Rev. 0 | Page 7 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE POWER DERATING CURVES ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL BYPASS A STATE INTERNAL AMPLIFIER STATE INTERNAL BYPASS STATE EXTERNAL BYPASS B STATE TEST CIRCUITS THEORY OF OPERATION SIGNAL PATH STATES FOR DIGITAL CONTROL INPUTS APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING During Power-Up During Power-Down EVALUATION PCB EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE