Datasheet HMC902LP3E (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 5 GHz to 11 GHz GaAs, pHEMT, MMIC, Low Noise Amplifier |
| Pages / Page | 13 / 10 — HMC902LP3E. Data Sheet. APPLICATIONS INFORMATION |
| Revision | E |
| File Format / Size | PDF / 413 Kb |
| Document Language | English |
HMC902LP3E. Data Sheet. APPLICATIONS INFORMATION
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HMC902LP3E Data Sheet APPLICATIONS INFORMATION
The HMC902LP3E has VGG1 and VGG2 optional gate bias pins. The recommended bias sequence during power-down is as fol ows: When these pads are left open, the amplifier runs in self biased 1. Turn off the RF signal. operation with typical IDQ = 80 mA. Figure 23 shows the basic 2. Decrease VGG1 and VGG2 to −2.0 V to achieve typical connections for operating the HMC902LP3E in self biased IDQ = 0 mA. operation mode. Both RFIN and RFOUT ports of HMC902LP3E 3. Decrease VDD1 and VDD2 to 0 V. have on-chip dc block capacitors, eliminating the need for 4. Increase VGG1 and VGG2 to 0 V. external ac coupling capacitors. The bias conditions previously listed (VDD = 3.5 V and IDQ = When using the optional VGG1 and VGG2 gate bias pins, use the 80 mA) are the recommended operating points to achieve recommended bias sequencing to prevent damage to the amplifier. optimum performance. The data used in this data sheet was The recommended bias sequence during power-up is as follows: taken with the recommended bias conditions. 1. Connect to GND. When using the HMC902LP3E with different bias conditions, 2. Set V different performance than what is shown in the Typical GG1 and VGG2 to −2.0 V. 3. Set V Performance Characteristics section can result. Decreasing the DD1 and VDD2 to 3.5 V. 4. Increase V V GG1 and VGG2 to achieve typical IDQ = 80 mA. DD level has negligible effect on gain and NF performance, but 5. Apply the RF signal. reduces the P1dB, see Figure 18. For applications where the P1dB requirement is not stringent, the HMC902LP3E can be down biased to reduce power consumption. Rev. E | Page 10 of 13 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD (PCB) APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
HMC902LP3E Data Sheet APPLICATIONS INFORMATION
The HMC902LP3E has VGG1 and VGG2 optional gate bias pins. The recommended bias sequence during power-down is as fol ows: When these pads are left open, the amplifier runs in self biased 1. Turn off the RF signal. operation with typical IDQ = 80 mA. Figure 23 shows the basic 2. Decrease VGG1 and VGG2 to −2.0 V to achieve typical connections for operating the HMC902LP3E in self biased IDQ = 0 mA. operation mode. Both RFIN and RFOUT ports of HMC902LP3E 3. Decrease VDD1 and VDD2 to 0 V. have on-chip dc block capacitors, eliminating the need for 4. Increase VGG1 and VGG2 to 0 V. external ac coupling capacitors. The bias conditions previously listed (VDD = 3.5 V and IDQ = When using the optional VGG1 and VGG2 gate bias pins, use the 80 mA) are the recommended operating points to achieve recommended bias sequencing to prevent damage to the amplifier. optimum performance. The data used in this data sheet was The recommended bias sequence during power-up is as follows: taken with the recommended bias conditions. 1. Connect to GND. When using the HMC902LP3E with different bias conditions, 2. Set V different performance than what is shown in the Typical GG1 and VGG2 to −2.0 V. 3. Set V Performance Characteristics section can result. Decreasing the DD1 and VDD2 to 3.5 V. 4. Increase V V GG1 and VGG2 to achieve typical IDQ = 80 mA. DD level has negligible effect on gain and NF performance, but 5. Apply the RF signal. reduces the P1dB, see Figure 18. For applications where the P1dB requirement is not stringent, the HMC902LP3E can be down biased to reduce power consumption. Rev. E | Page 10 of 13 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD (PCB) APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
