Datasheet ADTR1107 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 6 GHz to 18 GHz, Front-End IC |
| Pages / Page | 28 / 6 — ADTR1107. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating. … |
| Revision | A |
| File Format / Size | PDF / 943 Kb |
| Document Language | English |
ADTR1107. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating. THERMAL RESISTANCE. Table 7. Thermal Resistance1
Model Line for this Datasheet
Text Version of Document
link to page 28
ADTR1107 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6.
Stresses at or above those listed under Absolute Maximum
Parameter Rating
Ratings may cause permanent damage to the product. This is a Transmit State (PA On), Receive State Off stress rating only; functional operation of the product at these VDD_PA 5.5 V or any other conditions above those indicated in the operational VGG_PA −2 V to +0 V section of this specification is not implied. Operation beyond Continuous Wave (CW) RF Input Power 20 dBm the maximum operating conditions for extended periods may (RFIN) at TX_IN affect product reliability. Continuous Power Dissipation (PDISS) 1.71 W
THERMAL RESISTANCE
(TA = 85°C, Derate 18.98 mW/°C Above 85°C) Thermal performance is directly linked to printed circuit board Receive State (LNA On), Transmit State Off (PCB) design and operating environment. Careful attention to VDD_LNA 4 V PCB thermal design is required. VGG_LNA −2 V to +0.2 V θJC is the thermal resistance from the operating portion of the CW RFIN at ANT 20 dBm device to the outside surface of the package (case) closest to the PDISS (TA = 85°C, Derate 5.04 mW/°C 0.453 W device mounting area. Above 85°C) Transmit and Receive States
Table 7. Thermal Resistance1
Output Load Voltage Standing Wave 7:1
Package Type θJC Transmit State θJC Receive State Unit
Ratio (VSWR) CC-24-8 52.7 198.4 °C/W VDD_SW Range −0.3 V to +3.6 V 1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal VSS_SW Range −3.6 V to +0.3 V test board with 36 thermal vias. Refer to the JEDEC standard JESD51 for VDD_CTRL Range −0.3 V to VDD + 0.3 V additional information. Channel Temperature 175°C
ESD CAUTION
Maximum Peak Reflow Temperature 260°C (Moisture Sensitivity Level 3, MSL3)1 Storage Temperature Range −40°C to +125°C Operating Temperature Range −40°C to +85°C ESD Sensitivity (Human Body Model) Class 1B (Passed ±500 V) 1 See the Ordering Guide section for more information.
Table 8. Signal Path Truth Table State CTRL_SW RF Signal Path
Transmit Low TX_IN to ANT Receive High ANT to RX_OUT Rev. A | Page 6 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS TRANSMIT STATE RECEIVE STATE THEORY OF OPERATION APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING TYPICAL APPLICATION CIRCUIT INTERFACING THE ADTR1107 TO THE ADAR1000 X BAND AND KU BAND BEAMFORMER OUTLINE DIMENSIONS ORDERING GUIDE
ADTR1107 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6.
Stresses at or above those listed under Absolute Maximum
Parameter Rating
Ratings may cause permanent damage to the product. This is a Transmit State (PA On), Receive State Off stress rating only; functional operation of the product at these VDD_PA 5.5 V or any other conditions above those indicated in the operational VGG_PA −2 V to +0 V section of this specification is not implied. Operation beyond Continuous Wave (CW) RF Input Power 20 dBm the maximum operating conditions for extended periods may (RFIN) at TX_IN affect product reliability. Continuous Power Dissipation (PDISS) 1.71 W
THERMAL RESISTANCE
(TA = 85°C, Derate 18.98 mW/°C Above 85°C) Thermal performance is directly linked to printed circuit board Receive State (LNA On), Transmit State Off (PCB) design and operating environment. Careful attention to VDD_LNA 4 V PCB thermal design is required. VGG_LNA −2 V to +0.2 V θJC is the thermal resistance from the operating portion of the CW RFIN at ANT 20 dBm device to the outside surface of the package (case) closest to the PDISS (TA = 85°C, Derate 5.04 mW/°C 0.453 W device mounting area. Above 85°C) Transmit and Receive States
Table 7. Thermal Resistance1
Output Load Voltage Standing Wave 7:1
Package Type θJC Transmit State θJC Receive State Unit
Ratio (VSWR) CC-24-8 52.7 198.4 °C/W VDD_SW Range −0.3 V to +3.6 V 1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal VSS_SW Range −3.6 V to +0.3 V test board with 36 thermal vias. Refer to the JEDEC standard JESD51 for VDD_CTRL Range −0.3 V to VDD + 0.3 V additional information. Channel Temperature 175°C
ESD CAUTION
Maximum Peak Reflow Temperature 260°C (Moisture Sensitivity Level 3, MSL3)1 Storage Temperature Range −40°C to +125°C Operating Temperature Range −40°C to +85°C ESD Sensitivity (Human Body Model) Class 1B (Passed ±500 V) 1 See the Ordering Guide section for more information.
Table 8. Signal Path Truth Table State CTRL_SW RF Signal Path
Transmit Low TX_IN to ANT Receive High ANT to RX_OUT Rev. A | Page 6 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS TRANSMIT STATE RECEIVE STATE THEORY OF OPERATION APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING TYPICAL APPLICATION CIRCUIT INTERFACING THE ADTR1107 TO THE ADAR1000 X BAND AND KU BAND BEAMFORMER OUTLINE DIMENSIONS ORDERING GUIDE
