Datasheet HMC7229LS6 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | GaAs, pHEMT, MMIC, 1 W, Power Amplifier with Power Detector, 37 GHz to 40 GHz |
| Pages / Page | 15 / 5 — Data Sheet. HMC7229LS6. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. TOP … |
| Revision | E |
| File Format / Size | PDF / 328 Kb |
| Document Language | English |
Data Sheet. HMC7229LS6. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. TOP VIEW. (Not to Scale). T U. DD1. 11 VDD2. DD3. 10 VDD4. GG1. 9 VGG2
Model Line for this Datasheet
Text Version of Document
link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6
Data Sheet HMC7229LS6 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS HMC7229LS6 TOP VIEW (Not to Scale) T U F T D O D RE DE V GN RF GN V 16 15 14 13 12 V 1 DD1 11 VDD2 V 2 DD3 10 VDD4 V 3 GG1 9 VGG2 4 5 6 7 8 C D IN D C NI GN NI RF GN NOTES 1. NIC = NO INTERNAL CONNECTION. NOTE THAT DATA SHOWN HEREIN WAS MEASURED WITH THESE PINS EXTERNALLY CONNECTED TO RF/DC GROUND.
002
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND.
13337- Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1, 2, 10, 11 VDD1 to VDD4 Drain Bias Voltages. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF are required for each of these pins. See Figure 3. 3, 9 VGG1, VGG2 Gate Controls for the Power Amplifier. Adjust VGGx to achieve the recommended bias current. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF are required for each of these pins. Apply VGGx bias to either Pin 3 or Pin 9. See Figure 4. 4, 8 NIC No Internal Connection. Note that data shown herein was measured with these pins externally connected to RF/dc ground. 5, 7, 13, 15 GND Ground Pins. Connect these pins and the exposed ground pad to RF/dc ground. See Figure 5. 6 RFIN RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 6. 12 VDET Detector Voltage. This pin is the dc voltage that represents the RF output power rectified by the diode that is biased through an external resistor. See Figure 8. 14 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 9. 16 VREF Detector Reference Voltage. This pin is the dc voltage of the diode biased through an external resistor used for the temperature compensation of VDET. See Figure 7. EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground. Rev. E | Page 5 of 15 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCE During Power-Up During Power-Down EVALUATION PRINTED CIRCUIT BOARD (PCB) TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet HMC7229LS6 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS HMC7229LS6 TOP VIEW (Not to Scale) T U F T D O D RE DE V GN RF GN V 16 15 14 13 12 V 1 DD1 11 VDD2 V 2 DD3 10 VDD4 V 3 GG1 9 VGG2 4 5 6 7 8 C D IN D C NI GN NI RF GN NOTES 1. NIC = NO INTERNAL CONNECTION. NOTE THAT DATA SHOWN HEREIN WAS MEASURED WITH THESE PINS EXTERNALLY CONNECTED TO RF/DC GROUND.
002
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND.
13337- Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1, 2, 10, 11 VDD1 to VDD4 Drain Bias Voltages. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF are required for each of these pins. See Figure 3. 3, 9 VGG1, VGG2 Gate Controls for the Power Amplifier. Adjust VGGx to achieve the recommended bias current. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF are required for each of these pins. Apply VGGx bias to either Pin 3 or Pin 9. See Figure 4. 4, 8 NIC No Internal Connection. Note that data shown herein was measured with these pins externally connected to RF/dc ground. 5, 7, 13, 15 GND Ground Pins. Connect these pins and the exposed ground pad to RF/dc ground. See Figure 5. 6 RFIN RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 6. 12 VDET Detector Voltage. This pin is the dc voltage that represents the RF output power rectified by the diode that is biased through an external resistor. See Figure 8. 14 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 9. 16 VREF Detector Reference Voltage. This pin is the dc voltage of the diode biased through an external resistor used for the temperature compensation of VDET. See Figure 7. EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground. Rev. E | Page 5 of 15 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCE During Power-Up During Power-Down EVALUATION PRINTED CIRCUIT BOARD (PCB) TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE
