Datasheet AD8324 (Analog Devices) - 7

link to page 13 link to page 13
Data Sheet AD8324 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D N C D C E C N N X GND 1 V G C 20 GND G V T 0 9 2 1 81 71 61 V 2 19 CC VCC GND 3 18 TXEN GND 1 15 RAMP GND 4 17 RAMP GND 2 14 V AD8324 AD8324 OUT+ V 5 16 IN+ VOUT+ V 3 13 V TOP VIEW IN+ TOP VIEW OUT– V 6 (Not to Scale) V 4 (Not to Scale) 12 BYP 15 IN– V IN– OUT– GND 5 11 NIC GND 7 14 BYP DATEN 8 13 NIC 6 7 8 9 01 SDATA 9 12 SLEEP N A K D P E T L N E T CLK 10 A C E 11 GND A D G L D S S NOTES
-005
NOTES
0
1. NIC = NO INTERNAL CONNECTION. DO NOT CONNECT 1. NIC = NO INTERNAL CONNECTION.
9-
TO THIS PIN. DO NOT CONNECT TO THIS PIN.
433 0
2. THE EXPOSED PAD MUST BE CONNECTED TO A
-006
SOLID COPPER PLANE WITH A LOW THERMAL
0 9-
RESISTANCE. THIS APPLIES TO THE 20-LEAD LFCSP
433
PACKAGE ONLY.
0 Figure 5. 20-Lead LFCSP Pin Configuration Figure 6. 20-Lead QSOP Pin Configuration
Table 6. Pin Function Descriptions Pin No. 20-Lead LFCSP 20-Lead QSOP Mnemonic Description
1, 2, 5, 9, 18, 19 1, 3, 4, 7, 11, 20 GND Common External Ground Reference. 3 5 VIN+ Noninverting Input. DC-biased to approximately VCC/2. Must be ac-coupled with a 0.1 μF capacitor. 4 6 VIN– Inverting Input. DC-biased to approximately VCC/2. Must be ac-coupled with a 0.1 μF capacitor. 6 8 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0 to Logic 1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A Logic 1 to Logic 0 transition inhibits the data latch (holds the previous and simultaneously enables the register for serial data load). 7 9 SDATA Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the internal register with the most significant bit (MSB) first. 8 10 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave shift register. Logic 0 to Logic 1 transition latches the data bit, and a Logic 1 to Logic 0 transfers the data bit to the slave. This requires the input serial data-word to be valid at or before this clock transition. 10 12 SLEEP Low Power Sleep Mode. In sleep mode, the supply current of the AD8324 is reduced to 30 μA. A Logic 0 powers down the device (high ZOUT state), and a Logic 1 powers up the device. 11 13 NIC No Internal Connection. Do not connect to this pin. 12 14 BYP Internal Bypass. This pin must be externally decoupled (0.1 μF capacitor). 13 15 VOUT– Negative Output Signal. Must be biased to VCC. See Figure 23. 14 16 VOUT+ Positive Output Signal. Must be biased to VCC. See Figure 23. 15 17 RAMP External RAMP Capacitor (Optional). 16 18 TXEN Transmit Enable. Logic 0 disables forward transmission, and Logic 1 enables forward transmission. 17, 20 2, 19 VCC Common Positive External Supply Voltage. 0 Not applicable EPAD Exposed Pad. The exposed pad must be connected to a solid copper plane with low thermal resistance. This applies to the 20-lead LFCSP package only. Rev. C | Page 7 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE