Datasheet PMG1-S1 (Infineon) - 3
| Manufacturer | Infineon |
| Description | Power Delivery Microcontroller Gen1 |
| Pages / Page | 41 / 3 — PMG1-S1 Datasheet. Table 1. Comparison of Features of Different MCUs of … |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
PMG1-S1 Datasheet. Table 1. Comparison of Features of Different MCUs of the PMG1 Family. Sub-system or. Range. Item. PMG1-S0
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PMG1-S1 Datasheet
Table 1 shows the comparison of features of different MCUs of the PMG1 family.
Table 1. Comparison of Features of Different MCUs of the PMG1 Family Sub-system or Range Item PMG1-S0 PMG1-S1 PMG1-S2 PMG1-S3*
Core Arm Cortex-M0 Arm Cortex-M0 Arm Cortex-M0 Arm Cortex-M0+ CPU and Max Freq (MHz) 48 48 48 48 Memory Sub-system Flash (KB) 64 128 128 256 SRAM (KB) 8 12 8 32 Power Delivery Ports 1 1 1 1 port for 48-QFN 2 ports for 97-BGA Role Sink DRP DRP DRP Power Delivery MOSFET Gate Drivers 1x PFET 2x PFET 2x NFET Flexible 2x NFET VBUS OVP, UVP, and OCP. VBUS OVP, UVP, and OCP. Fault Protections VBUS OVP and UVP SCP and RCP (for Source VBUS OVP, UVP, SCP and RCP (for Source Configuration only). and OCP Configuration only). Integrated Full Speed USB USB 2.0 Device with No No Yes Yes Billboard Class Support Supply (V) VDDD (2.7–5.5) VSYS (2.75–5.5) VSYS (2.7–5.5) VSYS (2.8–5.5) Voltage Range VBUS (4–21.5) VBUS (4–21.5) VBUS (4–21.5) VBUS (4–28) IO (V) 1.71–5.5 1.71–5.5 1.71–5.5 1.71–5.5 7 for 48-QFN SCB (out of which only 5 can be (configurable as 2 4 4 configured as SPI and I2C/UART/SPI) UART) 8 for 97-BGA TCPWM Block Digital (configurable as timer, counter or pulse-width 4 2 4 7 for 48-QFN 8 for 97-BGA modulator) Yes Hardware (AES-128/192/256, Yes Authentication Block No No SHA1, SHA2-224, (AES-128, SHA2-256, (Crypto) SHA2-256, PRNG, TRNG, Vector Unit) CRC) ADC 2x 8-bit SAR 1x 8-bit SAR 2x 8-bit SAR 2x 8-bit SAR 1x 12-bit SAR Analog On-chip Temperature Sensor Yes Yes Yes Yes Direct Memory Access (DMA) DMA No No No Yes GPIO Max # of I/O 12 (10 + 2 OVT) 17 (15 + 2 OVT) 20 (18 + 2 OVT) 26 (24 + 2 OVT) for 48-QFN 50 (48 + 2 OVT) for 97-BGA Charging Standards BC 1.2, AC BC 1.2, AC BC 1.2, AC, AFC and Quick Charging Charge 3.0 Standards Charging Sink BC 1.2, Apple Charging (AC) BC 1.2, AC BC 1.2, AC BC 1.2, AC Yes Yes (up to ±8-kV Contact (up to ± 8-kV Contact Discharge, Yes Discharge, Yes ESD Protection ESD Protection up to ±15-kV Air up to ±15-kV Air Discharge, (Human Body Model and Discharge, (Human Body Model and Human Body Model, Charged Device Model) Human Body Model, Charged Device Model) and Charged Device and Charged Device Model) Model) *Contact your local Cypress sales office for more information on PMG1-S3. Document Number: 002-31597 Rev. *B Page 2 of 40 Document Outline PMG1-S1 Datasheet, Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S1 General Description Features USB-PD Type-C Legacy Charging (source and sink) Mux Integrated VBUS Load Switch Controller LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and PMG1 SDK Functional Overview USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC USB 2.0 Mux VBUS Discharge VBUS Regulator Gate Driver for VBUS PFET on Consumer Path Charger Detect High-Voltage Tolerant CC Lines VBUS Load Switch Controller for Provider Path RCP CSA Slew-Rate Controllable Gate Driver Overvoltage and Undervoltage Protection on VBUS Overcurrent Protection on VBUS True Random Number Generator CPU and Memory Subsystem CPU Flash SROM SRAM Peripherals Timer/Counter/PWM Block (TCPWM) GPIO Power System Overview Pinouts Application Diagrams Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter Charger Detect VSYS Switch CSA VBUS UV/OV Consumer Side PFET Gate Driver Provider Side PFET Gate Driver Provider Side PFET RCP DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
PMG1-S1 Datasheet
Table 1 shows the comparison of features of different MCUs of the PMG1 family.
Table 1. Comparison of Features of Different MCUs of the PMG1 Family Sub-system or Range Item PMG1-S0 PMG1-S1 PMG1-S2 PMG1-S3*
Core Arm Cortex-M0 Arm Cortex-M0 Arm Cortex-M0 Arm Cortex-M0+ CPU and Max Freq (MHz) 48 48 48 48 Memory Sub-system Flash (KB) 64 128 128 256 SRAM (KB) 8 12 8 32 Power Delivery Ports 1 1 1 1 port for 48-QFN 2 ports for 97-BGA Role Sink DRP DRP DRP Power Delivery MOSFET Gate Drivers 1x PFET 2x PFET 2x NFET Flexible 2x NFET VBUS OVP, UVP, and OCP. VBUS OVP, UVP, and OCP. Fault Protections VBUS OVP and UVP SCP and RCP (for Source VBUS OVP, UVP, SCP and RCP (for Source Configuration only). and OCP Configuration only). Integrated Full Speed USB USB 2.0 Device with No No Yes Yes Billboard Class Support Supply (V) VDDD (2.7–5.5) VSYS (2.75–5.5) VSYS (2.7–5.5) VSYS (2.8–5.5) Voltage Range VBUS (4–21.5) VBUS (4–21.5) VBUS (4–21.5) VBUS (4–28) IO (V) 1.71–5.5 1.71–5.5 1.71–5.5 1.71–5.5 7 for 48-QFN SCB (out of which only 5 can be (configurable as 2 4 4 configured as SPI and I2C/UART/SPI) UART) 8 for 97-BGA TCPWM Block Digital (configurable as timer, counter or pulse-width 4 2 4 7 for 48-QFN 8 for 97-BGA modulator) Yes Hardware (AES-128/192/256, Yes Authentication Block No No SHA1, SHA2-224, (AES-128, SHA2-256, (Crypto) SHA2-256, PRNG, TRNG, Vector Unit) CRC) ADC 2x 8-bit SAR 1x 8-bit SAR 2x 8-bit SAR 2x 8-bit SAR 1x 12-bit SAR Analog On-chip Temperature Sensor Yes Yes Yes Yes Direct Memory Access (DMA) DMA No No No Yes GPIO Max # of I/O 12 (10 + 2 OVT) 17 (15 + 2 OVT) 20 (18 + 2 OVT) 26 (24 + 2 OVT) for 48-QFN 50 (48 + 2 OVT) for 97-BGA Charging Standards BC 1.2, AC BC 1.2, AC BC 1.2, AC, AFC and Quick Charging Charge 3.0 Standards Charging Sink BC 1.2, Apple Charging (AC) BC 1.2, AC BC 1.2, AC BC 1.2, AC Yes Yes (up to ±8-kV Contact (up to ± 8-kV Contact Discharge, Yes Discharge, Yes ESD Protection ESD Protection up to ±15-kV Air up to ±15-kV Air Discharge, (Human Body Model and Discharge, (Human Body Model and Human Body Model, Charged Device Model) Human Body Model, Charged Device Model) and Charged Device and Charged Device Model) Model) *Contact your local Cypress sales office for more information on PMG1-S3. Document Number: 002-31597 Rev. *B Page 2 of 40 Document Outline PMG1-S1 Datasheet, Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S1 General Description Features USB-PD Type-C Legacy Charging (source and sink) Mux Integrated VBUS Load Switch Controller LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and PMG1 SDK Functional Overview USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC USB 2.0 Mux VBUS Discharge VBUS Regulator Gate Driver for VBUS PFET on Consumer Path Charger Detect High-Voltage Tolerant CC Lines VBUS Load Switch Controller for Provider Path RCP CSA Slew-Rate Controllable Gate Driver Overvoltage and Undervoltage Protection on VBUS Overcurrent Protection on VBUS True Random Number Generator CPU and Memory Subsystem CPU Flash SROM SRAM Peripherals Timer/Counter/PWM Block (TCPWM) GPIO Power System Overview Pinouts Application Diagrams Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter Charger Detect VSYS Switch CSA VBUS UV/OV Consumer Side PFET Gate Driver Provider Side PFET Gate Driver Provider Side PFET RCP DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
