Datasheet PMG1-S1 (Infineon) - 10

PMG1-S1 Datasheet
Functional Overview The RD resistor is used to identify PMG1-S1 as a Sink in a dual
role power (DRP) application. The dead battery RD resistor on
CC pins is required when the part is not powered for dead battery
termination detection and charging. USB-PD Subsystem (SS)
USB-PD Physical Layer
The PMG1-S1 USB-PD subsystem, as shown in Figure 3,
consists of the USB-PD physical layer (PHY) block and
supporting circuits. The PHY consists of a transmitter and
receiver that communicates using BMC and 4b/5b
encoded/decoded data over the CC channel based on the PD
3.0 specification. All communication is half-duplex. The PHY
practices collision avoidance to minimize communication errors
on the channel.
In addition, the PMG1-S1 USB-PD block includes all termination
resistors (RP and RD) and their switches as required by the USB
Type-C specification. RP and RD resistors are required for
connection detection, plug orientation detection, and for
establishing the USB source/sink roles.
The integrated RP resistor enables PMG1-S1 to be configured
as a Source. The RP resistor is implemented as a current source
and can be programmed to support the complete range of
current capacity on the VBUS defined in the USB Type-C spec. To support the latest USB-PD 3.0 specification, PMG1-S1
includes Fast Role Swap (FRS). The FRS feature enables
externally powered docks and hubs to rapidly switch to bus
power when their external power supply is removed.
For more details about FRS, refer to Section 6.3.19 in the
USB-PD 3.0 specification.
PMG1-S1 is designed to be fully interoperable with revision 3.0
of the USB Power Delivery specification as well as revision 2.0
of the USB Power Delivery specification.
PMG1-S1 supports Extended Messages containing data of up to
260 bytes. The Extended Messages will be larger than expected
by the USB-PD 2.0 hardware. To accommodate Revision 2.0
based systems, a Chunking mechanism is implemented such
that messages are limited to Revision 2.0 sizes unless it is
discovered that both systems support longer message lengths. Figure 3. USB-PD Subsystem
To/From System Resources
vref
iref
To/ from AHB 8-bit ADC From AMUX VCONN FET Enable VCONN_Source TxRx Enable VCONN
FETs Digital Baseband PHY
Tx_data
from AHB Enable Logic
Tx
SRAM 4b5b
Encoder SOP
Insert BMC
Encoder Rx_data
to AHB Rp TX CRC CC1 RX Rx
SRAM 4b5b
Decoder SOP
Detect CC2
Comp CC control
CC detect
Deep Sleep Reference Enable
Functional, Wakeup Interrupts Document Number: 002-31597 Rev. *B RD1 BMC
Decoder
Ref
Active
Rd DB
Rd RD2 Analog Baseband PHY
Deep Sleep Vref &
Iref Gen vref, iref RD1 is shorted to CC1 and RD2 is shorted to CC2 for DRP applications using
bondwire. For source applications, RD1 and RD2 are not shorted to CC1 and
CC2. Dead Battery (DB) RD termination is removed after MCU boots up Page 9 of 40