Datasheet PMG1-S1 (Infineon) - 4
| Manufacturer | Infineon |
| Description | Power Delivery Microcontroller Gen1 |
| Pages / Page | 41 / 4 — PMG1-S1 Datasheet. Table 1. Comparison of Features of Different MCUs of … |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
PMG1-S1 Datasheet. Table 1. Comparison of Features of Different MCUs of the PMG1 Family. Sub-system or. Range. Item. PMG1-S0
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PMG1-S1 Datasheet Table 1. Comparison of Features of Different MCUs of the PMG1 Family
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Sub-system or Range Item PMG1-S0 PMG1-S1 PMG1-S2 PMG1-S3*
48-pin QFN 24-pin QFN 40-pin QFN (6 × 6 mm, 0.5 mm pitch) Packages Package Options (4 × 4 mm, 0.5 mm 40-pin QFN (6 × 6 mm, 0.5 mm pitch) (6 × 6 mm, 0.5 mm pitch) pitch) 97-BGA (6 × 6 mm, 0.5 mm and 0.65 mm pitch) *Contact your local Cypress sales office for more information on PMG1-S3. The rest of this document discusses the PMG1-S1 device in detail. Document Number: 002-31597 Rev. *B Page 3 of 40 Document Outline PMG1-S1 Datasheet, Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S1 General Description Features USB-PD Type-C Legacy Charging (source and sink) Mux Integrated VBUS Load Switch Controller LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and PMG1 SDK Functional Overview USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC USB 2.0 Mux VBUS Discharge VBUS Regulator Gate Driver for VBUS PFET on Consumer Path Charger Detect High-Voltage Tolerant CC Lines VBUS Load Switch Controller for Provider Path RCP CSA Slew-Rate Controllable Gate Driver Overvoltage and Undervoltage Protection on VBUS Overcurrent Protection on VBUS True Random Number Generator CPU and Memory Subsystem CPU Flash SROM SRAM Peripherals Timer/Counter/PWM Block (TCPWM) GPIO Power System Overview Pinouts Application Diagrams Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter Charger Detect VSYS Switch CSA VBUS UV/OV Consumer Side PFET Gate Driver Provider Side PFET Gate Driver Provider Side PFET RCP DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
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Sub-system or Range Item PMG1-S0 PMG1-S1 PMG1-S2 PMG1-S3*
48-pin QFN 24-pin QFN 40-pin QFN (6 × 6 mm, 0.5 mm pitch) Packages Package Options (4 × 4 mm, 0.5 mm 40-pin QFN (6 × 6 mm, 0.5 mm pitch) (6 × 6 mm, 0.5 mm pitch) pitch) 97-BGA (6 × 6 mm, 0.5 mm and 0.65 mm pitch) *Contact your local Cypress sales office for more information on PMG1-S3. The rest of this document discusses the PMG1-S1 device in detail. Document Number: 002-31597 Rev. *B Page 3 of 40 Document Outline PMG1-S1 Datasheet, Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S1 General Description Features USB-PD Type-C Legacy Charging (source and sink) Mux Integrated VBUS Load Switch Controller LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and PMG1 SDK Functional Overview USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC USB 2.0 Mux VBUS Discharge VBUS Regulator Gate Driver for VBUS PFET on Consumer Path Charger Detect High-Voltage Tolerant CC Lines VBUS Load Switch Controller for Provider Path RCP CSA Slew-Rate Controllable Gate Driver Overvoltage and Undervoltage Protection on VBUS Overcurrent Protection on VBUS True Random Number Generator CPU and Memory Subsystem CPU Flash SROM SRAM Peripherals Timer/Counter/PWM Block (TCPWM) GPIO Power System Overview Pinouts Application Diagrams Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter Charger Detect VSYS Switch CSA VBUS UV/OV Consumer Side PFET Gate Driver Provider Side PFET Gate Driver Provider Side PFET RCP DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
