Datasheet ADG1414 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 9.5 Ω RON ±15 V/+12 V/±5 V iCMOS Serially-Controlled Octal SPST Switches |
| Pages / Page | 19 / 10 — ADG1414. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. SCLK … |
| Revision | B |
| File Format / Size | PDF / 536 Kb |
| Document Language | English |
ADG1414. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. SCLK 1. 24 SYNC. / T. 23 RESET/VL. DIN 3. 22 SDO. GND 4. 21 VSS. GND 1. 18 V
Model Line for this Datasheet
Text Version of Document
ADG1414 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS LV SCLK 1 24 SYNC / T K C E V 2 D L N S O DD 23 RESET/VL NI D C Y E D D V S S R S DIN 3 22 SDO 4 3 2 1 0 2 2 2 2 9 2 1 GND 4 21 VSS GND 1 18 V S1 5 20 S8 SS ADG1414 S1 2 17 S8 D1 6 19 D8 TOP VIEW D1 3 ADG1414 16 D8 (Not to Scale) S2 7 18 S7 S2 4 TOP VIEW 15 S7 (Not to Scale) D2 8 17 D7 D2 5 14 D7 S3 6 13 S3 S6 9 16 S6 D3 10 15 D6 7 8 9 01 11 21 3 4 4 5 5 6 S4 11 14 S5 D S D D S D
5 04
D4
0
12 13 D5
00 7-
NOTES
7- 49
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
849 08 0 Figure 4. TSSOP Pin Configuration Figure 5. LFCSP Pin Configuration
Table 9. Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description
1 22 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. 2 23 VDD Most Positive Power Supply Potential. 3 24 DIN Serial Data Input. This device has an 8-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 4 1 GND Ground (0 V) Reference. 5 2 S1 Source Terminal 1. This pin can be an input or an output. 6 3 D1 Drain Terminal 1. This pin can be an input or an output. 7 4 S2 Source Terminal 2. This pin can be an input or an output. 8 5 D2 Drain Terminal 2. This pin can be an input or an output. 9 6 S3 Source Terminal 3. This pin can be an input or an output. 10 7 D3 Drain Terminal 3. This pin can be an input or an output. 11 8 S4 Source Terminal 4. This pin can be an input or an output. 12 9 D4 Drain Terminal 4. This pin can be an input or an output. 13 10 D5 Drain Terminal 5. This pin can be an input or an output. 14 11 S5 Source Terminal 5. This pin can be an input or an output. 15 12 D6 Drain Terminal 6. This pin can be an input or an output. 16 13 S6 Source Terminal 6. This pin can be an input or an output. 17 14 D7 Drain Terminal 7. This pin can be an input or an output. 18 15 S7 Source Terminal 7. This pin can be an input or an output. 19 16 D8 Drain Terminal 8. This pin can be an input or an output. 20 17 S8 Source Terminal 8. This pin can be an input or an output. 21 18 VSS Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground. 22 19 SDO Serial Data Output. This pin can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. Pull this open-drain output to the supply with an external resistor. 23 20 RESET/VL RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5 V supply. Pull the pin low (<0.8 V) for a short period of time (15 ns is sufficient) to complete a hardware reset. All switches are opened, and the appropriate registers are cleared to 0. When using the RESET/VL pin to complete a hardware reset, all other SPI pins (SYNC, SCLK, and DIN) must be driven low. Rev. B | Page 10 of 19 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History Specifications ±15 V Dual Supply 12 V Single Supply ±5 V Dual Supply Continuous Current per Channel Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Serial Interface Input Shift Register Power-On Reset Daisy Chaining Outline Dimensions Ordering Guide
5 04
D4
0
12 13 D5
00 7-
NOTES
7- 49
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
849 08 0 Figure 4. TSSOP Pin Configuration Figure 5. LFCSP Pin Configuration
Table 9. Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description
1 22 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. 2 23 VDD Most Positive Power Supply Potential. 3 24 DIN Serial Data Input. This device has an 8-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 4 1 GND Ground (0 V) Reference. 5 2 S1 Source Terminal 1. This pin can be an input or an output. 6 3 D1 Drain Terminal 1. This pin can be an input or an output. 7 4 S2 Source Terminal 2. This pin can be an input or an output. 8 5 D2 Drain Terminal 2. This pin can be an input or an output. 9 6 S3 Source Terminal 3. This pin can be an input or an output. 10 7 D3 Drain Terminal 3. This pin can be an input or an output. 11 8 S4 Source Terminal 4. This pin can be an input or an output. 12 9 D4 Drain Terminal 4. This pin can be an input or an output. 13 10 D5 Drain Terminal 5. This pin can be an input or an output. 14 11 S5 Source Terminal 5. This pin can be an input or an output. 15 12 D6 Drain Terminal 6. This pin can be an input or an output. 16 13 S6 Source Terminal 6. This pin can be an input or an output. 17 14 D7 Drain Terminal 7. This pin can be an input or an output. 18 15 S7 Source Terminal 7. This pin can be an input or an output. 19 16 D8 Drain Terminal 8. This pin can be an input or an output. 20 17 S8 Source Terminal 8. This pin can be an input or an output. 21 18 VSS Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground. 22 19 SDO Serial Data Output. This pin can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. Pull this open-drain output to the supply with an external resistor. 23 20 RESET/VL RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5 V supply. Pull the pin low (<0.8 V) for a short period of time (15 ns is sufficient) to complete a hardware reset. All switches are opened, and the appropriate registers are cleared to 0. When using the RESET/VL pin to complete a hardware reset, all other SPI pins (SYNC, SCLK, and DIN) must be driven low. Rev. B | Page 10 of 19 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History Specifications ±15 V Dual Supply 12 V Single Supply ±5 V Dual Supply Continuous Current per Channel Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Serial Interface Input Shift Register Power-On Reset Daisy Chaining Outline Dimensions Ordering Guide
