Datasheet ADG406, ADG407, ADG426 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | LC2MOS 8-/16-Channel High Performance Analog Multiplexers |
| Pages / Page | 20 / 7 — ADG406/ADG407/ADG426. ADG426 TIMING DIAGRAMS. 50%. tOFF (RS). A0, A1, A2, … |
| Revision | B |
| File Format / Size | PDF / 394 Kb |
| Document Language | English |
ADG406/ADG407/ADG426. ADG426 TIMING DIAGRAMS. 50%. tOFF (RS). A0, A1, A2, (A3). 0.8V. SWITCH. OUTPUT
Model Line for this Datasheet
Text Version of Document
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ADG406/ADG407/ADG426 ADG426 TIMING DIAGRAMS 3V 3V WR 50% 50% RS 50% 50% 0V 0V tW tW tS tH tOFF (RS) 3V
9
2V V
00
A0, A1, A2, (A3) 0
6-
0.8V EN 0.8V
10
SWITCH
02
0
0 00
0V
6-
OUTPUT
02
0V
00 Figure 4. Timing Sequence for Latching the Switch Address and Enable Inputs Figure 5. Reset Pulse Width and Reset Turn Off Time Figure 4 shows the timing sequence for latching the switch Figure 5 shows the reset pulse width, trs, and the reset turn off address and enable inputs. The latches are level sensitive; time, tOFF (RS). therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This Note that all digital input signals rise and fall times are input data is latched on the rising edge of WR. measured from 10% to 90% of 3 V; tR = tF = 20 ns. Rev. B | Page 7 of 20 Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DUAL SUPPLY SINGLE SUPPLY ADG426 TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY OUTLINE DIMENSIONS ORDERING GUIDE
ADG406/ADG407/ADG426 ADG426 TIMING DIAGRAMS 3V 3V WR 50% 50% RS 50% 50% 0V 0V tW tW tS tH tOFF (RS) 3V
9
2V V
00
A0, A1, A2, (A3) 0
6-
0.8V EN 0.8V
10
SWITCH
02
0
0 00
0V
6-
OUTPUT
02
0V
00 Figure 4. Timing Sequence for Latching the Switch Address and Enable Inputs Figure 5. Reset Pulse Width and Reset Turn Off Time Figure 4 shows the timing sequence for latching the switch Figure 5 shows the reset pulse width, trs, and the reset turn off address and enable inputs. The latches are level sensitive; time, tOFF (RS). therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This Note that all digital input signals rise and fall times are input data is latched on the rising edge of WR. measured from 10% to 90% of 3 V; tR = tF = 20 ns. Rev. B | Page 7 of 20 Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DUAL SUPPLY SINGLE SUPPLY ADG426 TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY OUTLINE DIMENSIONS ORDERING GUIDE
