Preliminary Datasheet EPC23102 (Efficient Power Conversion) - 8

eGaN® FET DATASHEET
EPC23102 Thermal derating curves in Figure 8 are derived from measurement
Power Supplies – VIN , VDRV , VDD , and VBOOT
data. At ambient temperature of 25°C using topside heatsink, the EPC23102 IC is specified with an output current handling capability The EPC23102 IC only requires an external 5 V VDRV power supply. greater than 35 A operating at 1 MHz switching frequency with airflow Internal low side and high side power supplies, VDD and VBOOT, are greater than 500 LFM. But without the benefit of topside heatsink, the generated from the external supply via two series connected switches. same conditions at 1 MHz and 500 LFM, the current rating is reduced to Figure 9 shows the simplified circuit diagram of the different power 16 A at ambient temperature of 25°C showing the dramatic difference supplies inside the IC and their interaction with each other. of using the lower RθJC_top of the higher thermal conductive path.
Figure 9: Simplified circuit diagram of VIN , VDRV , VDD , and VBOOT Figure 8: Thermal Derating Curves for Output Current Rating of Power Supplies EPC23102 IC using EPC90147 Evaluation Board
VIN LSG
Airflow = 1000 LFM
45 V Sync DDON 40
Topside H 500 kHz
Q drive boot
ea 1 MHz
OFF drive 35
tsink 1.5 MHz
EN 30
)
V 25 DDON VBOOTON
(A
AGND
ADILO
20 VDRV V 15 Q BOOT SA QSB 10
No Heatsink
VDD 5 025 35 45 55 65 75 85 95 105 The internal supplies can be disabled to save quiescent power by
Ambient Temperature (°C)
turning off the series switch, QSA in Figure 9, with 5 V applied to the EN pin to engage chip shutdown mode. In this mode, minimum current is drawn from the external VDRV supply while VDD is open circuit. Whatever
Airflow = 500 LFM
charges remain within the VDD bypass capacitor will be discharged by 45 the chip internal circuits at nominal rate of 10 mA/CDD. 40
500 kHz 1 MHz
In the chip shutdown circuit, series switch (Q
T
SA) between VDRV and VDD is 35
opside Hea 1.5 MHz
turned off by internal disable circuit which itself derived its power from
tsink
30 VIN such that the chip draws a maximum up to 600 µA at 48 V from VIN
)
when shutdown mode is engaged. The minimum input voltage (VINmin) 25
(A
should be at least 10 V for the IC to be enabled. Below the minimum
AD
20
I LO
VIN the pass-transistor between VDRV and VDD will be off. Same condition 15 when VDD disable pin, EN, is connected to 5 V. 10 The series connected high voltage synchronous bootstrap FET, QSB in
No Heatsink
Figure 9, between VDD and VBOOT for the high side floating bootstrap 5 supply is activated only after the LS FET (Q2) is turned on to avoid 0 overcharging during deadtime. The use of GaN FET in the charging path 25 35 45 55 65 75 85 95 105 eliminates reverse recovery and reduces power dissipation. Another
Ambient Temperature (°C)
advantage is the lower dropout voltage of 100 to 200 mV from the synchronous FET versus typical Si bootstrap diode voltage of 0.6 V. With synchronous charging VBOOT is maintained closer to the VDD voltage, al owing the HS FET gate drive circuit to have similar gate drive current and delay performance as the LS FET gate drive circuit. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 8