Preliminary Datasheet EPC23102 (Efficient Power Conversion) - 10

eGaN® FET DATASHEET
EPC23102 During HS FET (Q1) or LS FET (Q2) turn-on transitions with hard switching The Undervoltage Lockout (UVLO) circuit from the high side internal conditions, the fast di/dt of the HS FET or LS FET coupled with the power VBOOT supply would turn off the HS logic path local y within the floating loop inductance (Vpeak = Lpower loop · di/dt) would cause a transient over- high side well to provide protection against low voltage level at the voltage spike above VIN or below PGND. The EPC23102 pinouts for floating bootstrap capacitor, CBOOT, during charging and discharging the three power bars (VIN, SW, PGND) are coupled with the design of phases from internal synchronous bootstrap circuit. optimal layout techniques to achieve minimized power loop inductance. When the V Together with SW switching rate tuning by R DD and VBOOT supplies are not charged sufficiently or DRV and RBOOT, the over- discharged to too low a voltage level, the logic path circuits would not voltage spikes can be control ed to less than +10 V above rail and -10 V work correctly. Even with no V below ground during hard switching transitions. DD or VBOOT voltage, the output FETs can still turn on due to leakage. The high side loss of VBOOT supply protection The EPC90147 Evaluation Board provides guidelines for PCB layout to will be activated to turn on the Qoff switch in Figure 13 to keep the HS use the EPC23102 in application circuits together with the Gerber files FET (Q1) in an active off state. The active turn off circuit is powered from and Bill of Material. To control SW switching rate and transients, 2.2 Ω VIN in this case. are used for both RDRV and RBOOT for high frequency DC-DC converter Similar circuit is triggered by the low side loss of V switching around 1 MHz and 4.7 Ω used for 100 kHz motor drive inverter DD supply to turn on the Qoff switch for the LS FET (Q2). In this case the active turn off circuit is applications. powered by the SW node voltage.
Protection Circuits Logic Inputs
EPC integrated eGaN FETs are very robust devices when operating within The EPC23102 IC is capable of interfacing to digital and analog control ers the recommended operating conditions, output current rating and ther- with 3.3 V or 5 V CMOS logic levels. The logic level translator at the frontend mal management techniques as described. Still there are inevitable power level- shifts the PWM signal, HS supplies sequencing at startup and brownout conditions where the power IN and LSIN respectively, to internal IC level to operate the logic, level shifting and gate drive circuits. Logic input supplies would go out of the recommended range or even a complete loss thresholds are 2.4 V minimum to trigger a “high” state and 0.8 V maximum of supply. A particular damaging condition could occur when VIN supply for a guaranteed “low” state. A hysteresis of 300 mV is built-in to increase is already fully charged but VDRV is at the startup phase or discharged due noise margin. to fault events. In these conditions the output FETs could be commanded on into high R For interfacing with analog control er operating from V DS(on) state with low gate drive voltage level. Or worse when CC = 12 V that V outputs a 12 V PWM signal, a resistor network in series should be inserted DRV is completely lost, either the HS FET or LS FET or both can turn-on due to the output FET leakage current, especial y at higher temperature. to divide the voltage to acceptable VIH level and limit the input current into This could cause a short circuit across the C the logic input pins HS IN capacitor. IN and LSIN which is clamped to the VDD supply by ESD protection network. The EPC23102 integrates protection circuits as shown in Figure 13 (below) and the Truth Table (page 6). Separate and independent high side (HSIN) and low side (LSIN) logic control inputs al ow external control ers to set fixed or adaptive deadtimes for optimal operating efficiency. Cross conduction lockout logic commands
Figure 13: Simplified circuit diagram of the protection circuits
both FETs off when logic inputs are both high. Figure 14 shows how the
against low voltage levels or complete loss of supplies
logic inputs interact with each other. Here the timing diagram applies with VIN the HS FET (Q1) and LS FET (Q2) in half-bridge configuration and current is in HSG the positive direction going out of the half-bridge. When HSIN and LSIN are logic high at same time, both Q1 and Q2 will shut off. A built-in deadtime HSOFF of 5 ns is added, after that current then commutates to Q2 in 3rd quadrant Qoff Active conduction and SW will be clamped at negative VSD voltage of Q2. VBOOT V turn-off OK circuits Q
Figure 14: EPC23102 Input-to-Output Timing Diagram
UVLO A INV
HSIN
SW
LSIN
The Power On Reset (POR) circuit from the low side internal VDD supply would turn off both HS and LS logic path when VDD voltage level is below their respective trip levels during rising and fal ing sequencing of the
SW
external VDRV supply when the IC is enabled. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 10