Datasheet SiC967 (Vishay) - 2
| Manufacturer | Vishay |
| Description | 4.5 V to 60 V Input, 6 A, MicroBRICK DC/DC Regulator Module |
| Pages / Page | 22 / 2 — SiC967. Fig. 2 - Efficiency vs. Output Current. Top View. Bottom View. … |
| File Format / Size | PDF / 847 Kb |
| Document Language | English |
SiC967. Fig. 2 - Efficiency vs. Output Current. Top View. Bottom View. Fig. 3 - Top View and Bottom View
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Text Version of Document
SiC967
www.vishay.com Vishay Siliconix
Fig. 2 - Efficiency vs. Output Current Top View Bottom View Fig. 3 - Top View and Bottom View
E E E E T E AS D T T AS AS AS O N D IN OOD IN IN CI GN OU OU PH G PH PH V V PH V BO V EN P I LIM A V V MO NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 45 PHASE 27 VOUT 46 PHASE 26 VOUT 57 47 V PHASE IN 25 VOUT 48 PHASE 24 VOUT 49 PHASE 23 VOUT 55 AGND 50 PHASE 22 VOUT 51 PHASE 56 21 VOUT 52 PGND PHASE 20 VOUT 53 PHASE 19 VOUT 54 PHASE 18 VOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 E E E IN D D V D E D S T T V GL DD FB GN GN f SW AS AS AS DR GN V GN SN OU AS OU P P V P A V V V PH PH PH PH
Fig. 4 - Pin Configuration (Top Transparent View) PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION
1 to 3, 7, 39, PHASE Return path of high side gate driver 42 to 54 4, 38, 40, 41, 57 VIN Power stage input voltage. Drain of high side MOSFET 5, 6, 11, 56 PGND Power ground 8 GL Low side MOSFET gate signal 9 VDD Bias supply for the IC. VDD is an LDO output, connect a 1 μF decoupling capacitor to AGND Supply voltage for internal gate driver. When using the internal LDO as a bias power supply, V 10 V DRV is DRV the LDO output. Connect a 4.7 μF decoupling capacitor to PGND 12, 34, 55 AGND Analog ground Feedback input for switching regulator used to program the output voltage - connect to an external 13 FB resistor divider from VOUT to AGND 14 fSW Set the on-time by connecting a resistor to AGND 15 Vsns Output voltage sense point for internal ripple injection components 16 to 29 VOUT Power output pins 30 NC Leave floating or connect to AGND 31 ILIM Set the current limit by connecting ILIM pin to AGND or VDD, or leaving floating 32 MODE Set various operation modes by connecting a resistor to AGND. See specification table for details Open-drain power good indicator - high impedance indicates power is good. An external pull-up 33 PGOOD resistor is required Enable pin. Tie high / low to enable / disable the IC accordingly. This is a high voltage compatible pin, 35 EN can be tied to 60 V Supply voltage for internal regulators V 36 V DD and VDRV. This pin should be tied to VIN, but can also be CIN connected to a lower supply voltage (> 5 V) to reduce losses in the internal linear regulators 37 BOOT High side driver bootstrap voltage S23-0680-Rev. C, 28-Aug-2023
2
Document Number: 76444 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Siliconix
Fig. 2 - Efficiency vs. Output Current Top View Bottom View Fig. 3 - Top View and Bottom View
E E E E T E AS D T T AS AS AS O N D IN OOD IN IN CI GN OU OU PH G PH PH V V PH V BO V EN P I LIM A V V MO NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 45 PHASE 27 VOUT 46 PHASE 26 VOUT 57 47 V PHASE IN 25 VOUT 48 PHASE 24 VOUT 49 PHASE 23 VOUT 55 AGND 50 PHASE 22 VOUT 51 PHASE 56 21 VOUT 52 PGND PHASE 20 VOUT 53 PHASE 19 VOUT 54 PHASE 18 VOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 E E E IN D D V D E D S T T V GL DD FB GN GN f SW AS AS AS DR GN V GN SN OU AS OU P P V P A V V V PH PH PH PH
Fig. 4 - Pin Configuration (Top Transparent View) PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION
1 to 3, 7, 39, PHASE Return path of high side gate driver 42 to 54 4, 38, 40, 41, 57 VIN Power stage input voltage. Drain of high side MOSFET 5, 6, 11, 56 PGND Power ground 8 GL Low side MOSFET gate signal 9 VDD Bias supply for the IC. VDD is an LDO output, connect a 1 μF decoupling capacitor to AGND Supply voltage for internal gate driver. When using the internal LDO as a bias power supply, V 10 V DRV is DRV the LDO output. Connect a 4.7 μF decoupling capacitor to PGND 12, 34, 55 AGND Analog ground Feedback input for switching regulator used to program the output voltage - connect to an external 13 FB resistor divider from VOUT to AGND 14 fSW Set the on-time by connecting a resistor to AGND 15 Vsns Output voltage sense point for internal ripple injection components 16 to 29 VOUT Power output pins 30 NC Leave floating or connect to AGND 31 ILIM Set the current limit by connecting ILIM pin to AGND or VDD, or leaving floating 32 MODE Set various operation modes by connecting a resistor to AGND. See specification table for details Open-drain power good indicator - high impedance indicates power is good. An external pull-up 33 PGOOD resistor is required Enable pin. Tie high / low to enable / disable the IC accordingly. This is a high voltage compatible pin, 35 EN can be tied to 60 V Supply voltage for internal regulators V 36 V DD and VDRV. This pin should be tied to VIN, but can also be CIN connected to a lower supply voltage (> 5 V) to reduce losses in the internal linear regulators 37 BOOT High side driver bootstrap voltage S23-0680-Rev. C, 28-Aug-2023
2
Document Number: 76444 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
