Datasheet MAX4091, MAX4092, MAX4094 (Maxim) - 8

Single/Dual/Quad, Micropower, Single-Supply, Rail-to-Rail Op Amps Detailed Description
match the effective resistance seen at each input. Connect resistor R3 between the noninverting input and The single MAX4091, dual MAX4092 and quad ground when using the op amp in an inverting configu- MAX4094 op amps combine excellent DC accuracy ration (Figure 2a); connect resistor R3 between the with rail-to-rail operation at both input and output. With noninverting input and the input signal when using the their precision performance, wide dynamic range at low op amp in a noninverting configuration (Figure 2b). supply voltages, and very low supply current, these op Select R3 to equal the parallel combination of R1 and amps are ideal for battery-operated equipment, indus- R2. High source resistances will degrade noise perfor- trial, and data acquisition and control applications. mance, due to the the input current noise (which is mul-
Applications Information
tiplied by the source resistance).
Rail-to-Rail Inputs and Outputs Input Stage Protection Circuitry
The MAX4091/MAX4092/MAX4094’s input common- The MAX4091/MAX4092/MAX4094 include internal pro- mode range extends 50mV beyond the positive and tection circuitry that prevents damage to the precision negative supply rails, with excellent common-mode input stage from large differential input voltages. This rejection. Beyond the specified common-mode range, protection circuitry consists of back-to-back diodes the outputs are guaranteed not to undergo phase between IN+ and IN- with two 1.7kΩ resistors in series reversal or latchup. Therefore, the MAX4091/MAX4092/ (Figure 3). The diodes limit the differential voltage MAX4094 can be used in applications with common- applied to the amplifiers’ internal circuitry to no more mode signals, at or even beyond the supplies, without than VF, where VF is the diodes’ forward-voltage drop the problems associated with typical op amps. (about 0.7V at +25°C). The MAX4091/MAX4092/MAX4094’s output voltage Input bias current for the ICs (±20nA) is specified for swings to within 15mV of the supplies with a 100kΩ small differential input voltages. For large differential load. This rail-to-rail swing at the input and the output input voltages (exceeding VF), this protection circuitry substantially increases the dynamic range, especially increases the input current at IN+ and IN-: in low-supply-voltage applications. Figure 1 shows the input and output waveforms for the MAX4092, config- V [( + ) − V ( − )] − V IN IN F
MAX4091/MAX4092/MAX4094
ured as a unity-gain noninverting buffer operating from INPUT CURRENT = 2 ✕ . 1 k 7 Ω a single 3V supply. The input signal is 3.0VP-P, a 1kHz sinusoid centered at 1.5V. The output amplitude is approximately 2.98VP-P.
Output Loading and Stability
Even with their low quiescent current of less than
Input Offset Voltage
130µA per op amp, the MAX4091/MAX4092/MAX4094 Rail-to-rail common-mode swing at the input is obtained are well suited for driving loads up to 1kΩ while main- by two complementary input stages in parallel, which taining DC accuracy. Stability while driving heavy feed a folded cascaded stage. The PNP stage is active capacitive loads is another key advantage over compa- for input voltages close to the negative rail, and the NPN rable CMOS rail-to-rail op amps. stage is active for input voltages close to the positive rail. In op amp circuits, driving large capacitive loads The offsets of the two pairs are trimmed. However, increases the likelihood of oscillation. This is especially there is some residual mismatch between them. This true for circuits with high-loop gains, such as a unity- mismatch results in a two-level input offset characteris- gain voltage follower. The output impedance and a tic, with a transition region between the levels occurring capacitive load form an RC network that adds a pole to at a common-mode voltage of approximately 1.3V the loop response and induces phase lag. If the pole above VEE. Unlike other rail-to-rail op amps, the transi- frequency is low enough—as when driving a large tion region has been widened to approximately 600mV capacitive load––the circuit phase margin is degraded, in order to minimize the slight degradation in CMRR leading to either an under-damped pulse response or caused by this mismatch. oscillation. The input bias currents of the MAX4091/MAX4092/ The MAX4091/MAX4092/MAX4094 can drive capacitive MAX4094 are typically less than 20nA. The bias current loads in excess of 2000pF under certain conditions flows into the device when the NPN input stage is (Figure 4). When driving capacitive loads, the greatest active, and it flows out when the PNP input stage is potential for instability occurs when the op amp is active. To reduce the offset error caused by input bias sourcing approximately 200µA. Even in this case, sta- current flowing through external source resistances, bility is maintained with up to 400pF of output capaci-
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