Datasheet MAX6701, MAX6701A, MAX6702, MAX6702A, MAX6703, MAX6703A, MAX6704, MAX6705, MAX6705A, MAX6706, MAX6706A, MAX6707, MAX6707A, MAX6708 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Low-Voltage, SOT23, µP Supervisors with Power-Fail In/Out, Manual Reset, and Watchdog Timer |
| Pages / Page | 12 / 8 — Standard- vs. A-Version Comparison. Manual Reset. Power-Fail Comparator. … |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
Standard- vs. A-Version Comparison. Manual Reset. Power-Fail Comparator. Watchdog Timer
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MAX6701-08/ Low-Voltage, SOT23 µP Supervisors with Power-Fail MAX6701A-03A/ In/Out, Manual Reset, and Watchdog Timer MAX6705A-07A
Standard- vs. A-Version Comparison
threshold, WDO goes low whether or not the watchdog The MAX6701/MAX6702/MAX6703/MAX6705/MAX6706/ timer has timed out. Normally this would trigger an NMI, MAX6707s’ WDO latches low when one of the following but RESET goes low simultaneously, and thus overrides events occurs: the NMI. ● The watchdog timer times out (1.6s, typ). The MAX6704 watchdog circuit does not have an inde- pendent watchdog output (WDO). If the µP does not ● VCC, RST_IN1, or RST_IN2 is below its reset toggle the watchdog input within 1.6s, the MAX6704 threshold. asserts a reset output pulse for the reset timeout period. ● MR is pulled low.
Manual Reset
● WDO only deasserts with a valid WDI transition. The manual reset input (MR) allows reset to be The MAX6701(A)/MAX6702(A)/MAX6703(A)/MAX6705(A)/ triggered by a pushbutton switch. The switch is MAX6706(A)/ MAX6707(A)s’ WDO asserts when either effectively debounced by the reset pulse width. MR is VCC, RST_IN1, or RST_IN2 is below its reset thresh- CMOS logic compatible, so it can be driven by an external old. WDO deasserts without a timeout delay when the logic line. MR can be used to force a watchdog timeout to undervoltage situation has expired. WDO is latched low generate a reset pulse in the MAX6701(A)/MAX6702(A)/ when the watchdog timer elapses without seeing a WDI MAX6703(A)/MAX6705(A)/MAX6706(A)/MAX6707(A) by transition. WDO deasserts with a valid WDI transition connecting WDO to MR. OR by pulling MR low. See Figures 4 and 5 for standard-version timing. See
Power-Fail Comparator
Figures 6 and 7 for A-version timing. The uncommitted power-fail comparator can be used for various purposes because its noninverting input and
Watchdog Timer
output are externally available. The inverting input is The MAX6701
–
MAX6707 watchdog circuit monitors the internally connected to a 0.62V reference. To build an µP’s activity. If the µP does not toggle the WDI within 1.6s, early warning circuit for power failure, connect the PFI WDO goes low. When RESET is asserted, the watchdog pin to a voltage-divider (see the Typical Operating timer stays cleared and does not count. As soon as reset Circuit). Choose the voltage-divider ratio so that the is released, the timer starts counting. WDO deasserts voltage at PFI falls below 0.62V just before the regulator after a valid transition is detected at WDI. Pulses as short drops out. Use PFO to interrupt the µP so it can prepare as 50ns can be detected. for an orderly power-down. The low-input current at this Typically, WDO is connected to the NMI input of a µP. pin allows for large resistor values in the divider. When VCC, RST_IN1, or RST_IN2 drop below the reset tWD tWDI tWD VTH VTH +5V VCC WDI t 0V RP tRP +5V +5V WDO 0V RESET 0V +5V RESET +5V 0V MR RESET EXTERNALLY tRP TRIGGERED BY MR 0V +5V tMD (RESET) 0V tMR +5V +5V MR WDO 0V 0V ( ) ARE FOR MAX6702/MAX6706 ONLY. Figure 5. MAX6701/MAX6702/MAX6703/MAX6705/MAX6706/ Figure 6. MAX6701(A)/MAX6702(A)/MAX6703(A)/ MAX6707 Watchdog MAX6705(A)/ MAX6706(A)/MAX6707(A) RESET, MR, and WDO Timing with WDI Three-Stated www.maximintegrated.com Maxim Integrated │ 8
Standard- vs. A-Version Comparison
threshold, WDO goes low whether or not the watchdog The MAX6701/MAX6702/MAX6703/MAX6705/MAX6706/ timer has timed out. Normally this would trigger an NMI, MAX6707s’ WDO latches low when one of the following but RESET goes low simultaneously, and thus overrides events occurs: the NMI. ● The watchdog timer times out (1.6s, typ). The MAX6704 watchdog circuit does not have an inde- pendent watchdog output (WDO). If the µP does not ● VCC, RST_IN1, or RST_IN2 is below its reset toggle the watchdog input within 1.6s, the MAX6704 threshold. asserts a reset output pulse for the reset timeout period. ● MR is pulled low.
Manual Reset
● WDO only deasserts with a valid WDI transition. The manual reset input (MR) allows reset to be The MAX6701(A)/MAX6702(A)/MAX6703(A)/MAX6705(A)/ triggered by a pushbutton switch. The switch is MAX6706(A)/ MAX6707(A)s’ WDO asserts when either effectively debounced by the reset pulse width. MR is VCC, RST_IN1, or RST_IN2 is below its reset thresh- CMOS logic compatible, so it can be driven by an external old. WDO deasserts without a timeout delay when the logic line. MR can be used to force a watchdog timeout to undervoltage situation has expired. WDO is latched low generate a reset pulse in the MAX6701(A)/MAX6702(A)/ when the watchdog timer elapses without seeing a WDI MAX6703(A)/MAX6705(A)/MAX6706(A)/MAX6707(A) by transition. WDO deasserts with a valid WDI transition connecting WDO to MR. OR by pulling MR low. See Figures 4 and 5 for standard-version timing. See
Power-Fail Comparator
Figures 6 and 7 for A-version timing. The uncommitted power-fail comparator can be used for various purposes because its noninverting input and
Watchdog Timer
output are externally available. The inverting input is The MAX6701
–
MAX6707 watchdog circuit monitors the internally connected to a 0.62V reference. To build an µP’s activity. If the µP does not toggle the WDI within 1.6s, early warning circuit for power failure, connect the PFI WDO goes low. When RESET is asserted, the watchdog pin to a voltage-divider (see the Typical Operating timer stays cleared and does not count. As soon as reset Circuit). Choose the voltage-divider ratio so that the is released, the timer starts counting. WDO deasserts voltage at PFI falls below 0.62V just before the regulator after a valid transition is detected at WDI. Pulses as short drops out. Use PFO to interrupt the µP so it can prepare as 50ns can be detected. for an orderly power-down. The low-input current at this Typically, WDO is connected to the NMI input of a µP. pin allows for large resistor values in the divider. When VCC, RST_IN1, or RST_IN2 drop below the reset tWD tWDI tWD VTH VTH +5V VCC WDI t 0V RP tRP +5V +5V WDO 0V RESET 0V +5V RESET +5V 0V MR RESET EXTERNALLY tRP TRIGGERED BY MR 0V +5V tMD (RESET) 0V tMR +5V +5V MR WDO 0V 0V ( ) ARE FOR MAX6702/MAX6706 ONLY. Figure 5. MAX6701/MAX6702/MAX6703/MAX6705/MAX6706/ Figure 6. MAX6701(A)/MAX6702(A)/MAX6703(A)/ MAX6707 Watchdog MAX6705(A)/ MAX6706(A)/MAX6707(A) RESET, MR, and WDO Timing with WDI Three-Stated www.maximintegrated.com Maxim Integrated │ 8
