Datasheet MAX6701, MAX6701A, MAX6702, MAX6702A, MAX6703, MAX6703A, MAX6704, MAX6705, MAX6705A, MAX6706, MAX6706A, MAX6707, MAX6707A, MAX6708 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Low-Voltage, SOT23, µP Supervisors with Power-Fail In/Out, Manual Reset, and Watchdog Timer |
| Pages / Page | 12 / 9 — Reset Input. Monitoring Other System Voltages. Applications Information. … |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
Reset Input. Monitoring Other System Voltages. Applications Information. Ensuring a Valid RESET Output
Model Line for this Datasheet
Text Version of Document
MAX6701-08/ Low-Voltage, SOT23 µP Supervisors with Power-Fail MAX6701A-03A/ In/Out, Manual Reset, and Watchdog Timer MAX6705A-07A tWDI tWD tWD +5V WDI tWD MAX6701(A)– 0V V MAX6708 EXTERNAL +5V R1 WDO PFI, RST_IN1, OR RST_IN2 0V +5V R2 RESET 0V 0.62V tRP +5V (RESET) 0V +5V VEXT-TH = (1 + R1) x 0.62V R1 = R2 x R2 (VEXT-TH - 1) 0.62 MR 0V WHERE VEXT-TH IS THE EXTERNAL VOLTAGE TRIP LEVEL. ( ) ARE FOR MAX6702(A)/MAX6706(A) ONLY. Figure 7. MAX6701(A)/MAX6702(A)/MAX6703(A)/ Figure 8. Calculating Adjustable Voltage Thresholds MAX6705(A)/ MAX6706(A)/MAX6707(A) Watchdog Timing
Reset Input Monitoring Other System Voltages
The MAX6701(A)/MAX6702(A)/MAX6703(A) include two Other systems can be monitored by connecting a adjustable reset inputs for monitoring up to a total of voltage-divider to PFI and adjusting the ratio appropriately. three system voltages (including VCC). The thresholds In noisy systems, a capacitor between PFI and GND for the monitored RST_IN supplies are externally set reduces the power-fail circuit’s sensitivity to high- with resistor-divider networks (Figure 8). The reset frequency noise on the line being monitored. Reset can output is asserted if any of the monitored supplies (VCC, be asserted on other voltages in addition to the VCC RST_IN1, or RST_IN2) go below its specified threshold supply line. Connect PFO to MR to initiate a reset out- and remains asserted for the reset timeout period after put pulse when PFI drops below 0.62V. Figure 10 all supplies are above their thresholds. shows the MAX6704
–
MAX6708 configured to assert a reset output when the secondary supply falls below the
Applications Information
reset threshold.
Ensuring a Valid RESET Output Generating a Reset from Watchdog Overflow Down to VCC = 0
Connect WDO to MR to force a watchdog timeout to gen- When VCC falls below 1V, the MAX6701
–
MAX6708 erate a reset pulse for only the reset timeout period on the RESET output no longer sinks current; it becomes an MAX6701(A)/MAX6702(A)/MAX6703(A)/MAX6705(A)/ open circuit. High-impedance CMOS logic inputs can MAX6706(A)/MAX6707(A). When the MAX6704 watch- drift to undetermined voltages if left undriven. If a pull- dog times out, reset outputs are automatically asserted down resistor is added to the RESET pin, as shown (no external connections required). For the MAX6701/ in Figure 9, any stray charge or leakage currents are MAX6702/MAX6703/MAX6705/MAX6706/MAX6707 non-A drained to ground, holding RESET low. A resistor value versions, do not connect WDO to MR; this creates a (R1) is not critical; 100kΩ is large enough not to load locked condition. RESET and small enough to pull RESET to ground. This application works for push-pull output only (not for open-drain resets). www.maximintegrated.com Maxim Integrated │ 9
Reset Input Monitoring Other System Voltages
The MAX6701(A)/MAX6702(A)/MAX6703(A) include two Other systems can be monitored by connecting a adjustable reset inputs for monitoring up to a total of voltage-divider to PFI and adjusting the ratio appropriately. three system voltages (including VCC). The thresholds In noisy systems, a capacitor between PFI and GND for the monitored RST_IN supplies are externally set reduces the power-fail circuit’s sensitivity to high- with resistor-divider networks (Figure 8). The reset frequency noise on the line being monitored. Reset can output is asserted if any of the monitored supplies (VCC, be asserted on other voltages in addition to the VCC RST_IN1, or RST_IN2) go below its specified threshold supply line. Connect PFO to MR to initiate a reset out- and remains asserted for the reset timeout period after put pulse when PFI drops below 0.62V. Figure 10 all supplies are above their thresholds. shows the MAX6704
–
MAX6708 configured to assert a reset output when the secondary supply falls below the
Applications Information
reset threshold.
Ensuring a Valid RESET Output Generating a Reset from Watchdog Overflow Down to VCC = 0
Connect WDO to MR to force a watchdog timeout to gen- When VCC falls below 1V, the MAX6701
–
MAX6708 erate a reset pulse for only the reset timeout period on the RESET output no longer sinks current; it becomes an MAX6701(A)/MAX6702(A)/MAX6703(A)/MAX6705(A)/ open circuit. High-impedance CMOS logic inputs can MAX6706(A)/MAX6707(A). When the MAX6704 watch- drift to undetermined voltages if left undriven. If a pull- dog times out, reset outputs are automatically asserted down resistor is added to the RESET pin, as shown (no external connections required). For the MAX6701/ in Figure 9, any stray charge or leakage currents are MAX6702/MAX6703/MAX6705/MAX6706/MAX6707 non-A drained to ground, holding RESET low. A resistor value versions, do not connect WDO to MR; this creates a (R1) is not critical; 100kΩ is large enough not to load locked condition. RESET and small enough to pull RESET to ground. This application works for push-pull output only (not for open-drain resets). www.maximintegrated.com Maxim Integrated │ 9
