Datasheet ADRF5010 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Silicon SPST Switch, NonReflective, 100 MHz to 55 GHz |
| Pages / Page | 12 / 10 — ADRF5010. THEORY OF OPERATION. RF INPUT AND OUTPUT. Table 7. Control … |
| File Format / Size | PDF / 665 Kb |
| Document Language | English |
ADRF5010. THEORY OF OPERATION. RF INPUT AND OUTPUT. Table 7. Control Voltage Truth Table. Digital Control Input. RFx Paths. CTRL
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ADRF5010 THEORY OF OPERATION
The ADRF5010 can interface CMOS-/LVTTL-compatible control The power handling of the ADRF5010 derates with frequency below interfaces directly. 0.1 GHz. For derating of the RF power toward lower frequencies, see Figure 2. CTRL determines which RF ports are in the insertion loss state and in the isolation state. For the control voltage truth table, see Table 7. The ADRF5010 requires a positive supply voltage applied to the V
RF INPUT AND OUTPUT
DD pin and a negative supply voltage applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to The RF ports (RF1 and RF2) are DC-coupled to 0 V and no DC minimize RF coupling. blocking is required at the RF ports when the RF line potential is The ideal power-up sequence is as follows: equal to 0 V.
1.
Connect GND. The RF ports are internally matched to 50 Ω. However, impedance
2.
Power up V matching on transmission lines can be used to improve insertion DD and VSS. Power up VSS after VDD to avoid current transients on V loss and return loss performances at high frequencies. DD during ramp-up.
3.
Power up the digital control inputs. The relative order of the log- The ADRF5010 is bidirectional with equal power handling capabili- ic control inputs is not important. However, powering the digital ties. control inputs before the VDD supply can inadvertently forward The insertion loss path conducts the RF signal between the RF1 bias and damage the internal ESD protection structures. and RF2 ports. The isolation path provides high loss between RF1
4.
Apply signals to the RF input ports. and RF2 ports which are 50 Ω terminated.
Table 7. Control Voltage Truth Table Digital Control Input RFx Paths CTRL RF1 to RF2
Low Insertion loss (on) High Isolation (off)
analog.com Rev. 0 | 10 of 12
Document Outline Features Applications Functional Block Diagram General Description Specifications Single-Supply Operation Absolute Maximum Ratings Thermal Resistance Power Derating Curves Electrostatıc Dıscharge (ESD) Ratıngs ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Insertion Loss, Return Loss, and Isolation Input Power Compression and Third-Order Intercept Theory of Operation RF Input And Output Applications Information Evaluation Board Recommendatıons For Printed Circuit Board Design Outline Dimensions Ordering Guide Evaluation Boards
ADRF5010 THEORY OF OPERATION
The ADRF5010 can interface CMOS-/LVTTL-compatible control The power handling of the ADRF5010 derates with frequency below interfaces directly. 0.1 GHz. For derating of the RF power toward lower frequencies, see Figure 2. CTRL determines which RF ports are in the insertion loss state and in the isolation state. For the control voltage truth table, see Table 7. The ADRF5010 requires a positive supply voltage applied to the V
RF INPUT AND OUTPUT
DD pin and a negative supply voltage applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to The RF ports (RF1 and RF2) are DC-coupled to 0 V and no DC minimize RF coupling. blocking is required at the RF ports when the RF line potential is The ideal power-up sequence is as follows: equal to 0 V.
1.
Connect GND. The RF ports are internally matched to 50 Ω. However, impedance
2.
Power up V matching on transmission lines can be used to improve insertion DD and VSS. Power up VSS after VDD to avoid current transients on V loss and return loss performances at high frequencies. DD during ramp-up.
3.
Power up the digital control inputs. The relative order of the log- The ADRF5010 is bidirectional with equal power handling capabili- ic control inputs is not important. However, powering the digital ties. control inputs before the VDD supply can inadvertently forward The insertion loss path conducts the RF signal between the RF1 bias and damage the internal ESD protection structures. and RF2 ports. The isolation path provides high loss between RF1
4.
Apply signals to the RF input ports. and RF2 ports which are 50 Ω terminated.
Table 7. Control Voltage Truth Table Digital Control Input RFx Paths CTRL RF1 to RF2
Low Insertion loss (on) High Isolation (off)
analog.com Rev. 0 | 10 of 12
Document Outline Features Applications Functional Block Diagram General Description Specifications Single-Supply Operation Absolute Maximum Ratings Thermal Resistance Power Derating Curves Electrostatıc Dıscharge (ESD) Ratıngs ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Insertion Loss, Return Loss, and Isolation Input Power Compression and Third-Order Intercept Theory of Operation RF Input And Output Applications Information Evaluation Board Recommendatıons For Printed Circuit Board Design Outline Dimensions Ordering Guide Evaluation Boards
