Datasheet SG-8002CE (Epson) - 5

Crystal oscillator
SG-8002 series Jitter specifications and characteristics chart
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PLL-PLL connection
The SG-8002 series contains a PLL circuit and there are a few cases where the jitter value may be increased when this product is connected to another PLL oscillator (cascading connection). We do not recommend this series for analog video clock use and telecommunication synchronization. Please check in advance if the SG-8002 series jitter is acceptable to your application. (Jitter specification of the SG-8002 series is max.250 ps/CL=15 pF)
Jitter Specifications Supply Model Jitter Item Specifications Remarks Voltage
150 ps Max. 33 MHz  f0  125 MHz, L_CMOS=15 pF Cycle to cycle PT / PH 200 ps Max. 1.0 MHz  f0 < 33 MHz, L_CMOS=15 pF 5.0 V 0.5 V ST / SH 200 ps Max. 33 MHz  f0  125 MHz, L_CMOS=15 pF Peak to peak 250 ps Max. 1.0 MHz  f0 < 33 MHz, L_CMOS=15 pF Cycle to cycle 200 ps Max. 1.0 MHz  f0  125 MHz, L_CMOS=15 pF SC / PC 3.3 V 0.3 V Peak to peak 250 ps Max. 1.0 MHz  f0  125 MHz, L_CMOS=15 pF ■
Remarks on noise management for power supply line
It is not recommended to insert filters or other devices in the power supply line as a counter measure for EMI noise reduction. This may cause high-frequency impedance of the power supply line and negatively affect stable oscillation. When using this measure please evaluate the circuitry and device behavior in the circuit to verify and effects on oscillation. Start up time (0 % VCC to 90 % VCC) of power source should be more than 150 s. ■
SG-8002 series Characteristics chart
Current consumption Output Rise time (CMOS Level) (VCC=5.0V) 50 Symmetry 5.0 V CMOS Level 3.0 60 25 2 p 5 F p 40 F ) 4.5 V 55 2.5 3.0 V 5.0 V (% 3.3 V A) 30 5.5 V ry 15 pF ) 3.6 V t s (m e 50 50 pF (n 2.0 CC 20 m 2.7 V I e m mit 10 Sy 45 e si 1.5 R 40 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 Frequency(MHz) 1.0 Frequency(MHz) 10 15 20 25 30 35 40 45 50 55 Disable Current (VCC=5.0V) 50 Symmetry 3.3 V CMOS Level Load capacitance (pF) 60 Output Fall time (CMOS Level) 3.0 40 ) 55 4.5 V (% 30 pF 3.0 V 5.0 V A) 30 ryt 2.5 ) 3.3 V 5.5 V (m s e 50 s 3.6 V i d m 15 pF (n _ 20 I m e Sy 45 m 2.0 2.7 V 10 Ti ll 40 Fa 1.5 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 Frequency(MHz) Frequency(MHz) Stand-by Current 1.0 50 Symmetry 5.0V TTL Level 60 10 15 20 25 30 35 40 45 50 55 Load capacitance (pF) 40 ) 55 Output Rise time (TTL Level) 25 pF 2.0 A) (%  30 15 pF ry ( t 50 ) s td e 4.5 V s (n 1.5 _ 20 I m e 5.0 V m m 5.5 V 10 Sy 45 Ti e 1.0 si 40 R 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 20 40 60 80 100 120 140 VCC (V) Frequency(MHz) 10 15 20 25 30 Load capacitance (pF) Output load vs. Additional Current consumption Voltage coefficient [ VCC vs I_dis,I_std ] 20 2.0 Output Fall time (TTL Level) V 2.0 CC=5.0 V 18 1.8 I_dis(Va)=Times(Va)×I_dis(5.0V) 25 pF A) 16 1.6 I_std(Va)=Times(Va)×I_std(5.0V) 14 (m 50 pF 1.4 ) s e 12 u 15 pF s 1.2 1.5 (n l 4.5 V 10 e 1.0 e 5.0 V Va m l 8 30 pF m Ti 0.8 5.5 V a Ti n 6 0.6 ll 1.0 oiti 4 0.4 Fa d 2 0.2 Ad 0 20 40 60 80 100 120 140 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 10 15 20 25 30 Frequency(MHz) VCC (V) Load capacitance (pF) Document Outline SG-8002series_E187.pdf QMEMS_E152