Opening the door to “10 nm-class DRAM” for the first time in the industry after overcoming technical challenges in DRAM scaling
Samsung Electronics announced that it has begun mass producing the industry’s first 10-nanometer (nm) class* , 8-gigabit (Gb) DDR4 (double-data-rate-4) DRAM chips and the modules derived from them. DDR4 is quickly becoming the most widely produced memory for personal computers and IT networks in the world, and Samsung’s latest advancement will help to accelerate the industry-wide shift to advanced DDR4 products.
Samsung opened the door to “10 nm-class DRAM” for the first time in the industry after overcoming technical challenges in DRAM scaling. These challenges were mastered using currently available ArF (argon fluoride) immersion lithography, free from the use of EUV (extreme ultra violet) equipment.
Samsung’s roll-out of the 10 nm-class (1x) DRAM marks yet another milestone for the company after it first mass produced 20-nanometer (nm) 4Gb DDR3 DRAM in 2014.
Samsung’s leading-edge 10 nm-class 8 Gb DDR4 DRAM significantly improves the wafer productivity of 20 nm 8 Gb DDR4 DRAM by more than 30 percent.
The new DRAM supports a data transfer rate of 3,200 megabits per second (Mbps), which is more than 30 percent faster than the 2,400 Mbps rate of 20 nm DDR4 DRAM. Also, new modules produced from the 10 nm-class DRAM chips consume 10 to 20 percent less power, compared to their 20 nm-process-based equivalents, which will improve the design efficiency of next-generation, high-performance computing (HPC) systems and other large enterprise networks, as well as being used for the PC and mainstream server markets.
The industry-first 10 nm-class DRAM is the result of Samsung’s advanced memory design and manufacturing technology integration. To achieve an extremely high level of DRAM scalability, Samsung has taken its technological innovation one step further than what was used for 20 nm DRAM. Key technology developments include improvements in proprietary cell design technology, QPT (quadruple patterning technology) lithography, and ultra-thin dielectric layer deposition.
Unlike NAND flash memory, in which a single cell consists of only a transistor, each DRAM cell requires a capacitor and a transistor that are linked together, usually with the capacitor being placed on top of the area where the transistor rests. In the case of the new 10 nm-class DRAM, another level of difficulty is added because they have to stack very narrow cylinder-shaped capacitors that store large electric charges, on top of a few dozen nanometer-wide transistors, creating more than eight billion cells.
Samsung successfully created the new 10 nm-class cell structure by utilizing a proprietary circuit design technology and quadruple patterning lithography. Through quadruple patterning, which enables use of existing photolithography equipment, Samsung also built the core technological foundation for the development of the next-generation 10 nm-class DRAM (1y).
In addition, the use of a refined dielectric layer deposition technology enabled further performance improvements in the new 10 nm-class DRAM. Samsung engineers applied ultra-thin dielectric layers with unprecedented uniformity to a thickness of a mere single-digit angstrom (one 10 billionth of a meter) on cell capacitors, resulting in sufficient capacitance for higher cell performance.
Based on its advancements with the new 10 nm-class DDR4 DRAM, Samsung expects to also introduce a 10 nm-class mobile DRAM solution with high density and speed later this year, which will further solidify its leadership in the Ultra-HD smartphone market.
While introducing a wide array of 10 nm-class DDR4 modules with capacities ranging from 4 GB for notebook PCs to 128 GB for enterprise servers, Samsung will be extending its 20 nm DRAM line-up with its new 10 nm-class DRAM portfolio throughout the year.
