Analog Devices announced the availability of its new ADIsimCLKTM clock IC design and simulation tool. ADIsimCLK offers clock and timing engineers an easy-to-use simulation tool for designing and analyzing clock circuits used in a broad range of applications, such as wireless transceivers, broadband infrastructure, medical imaging, general instrumentation, and automated test equipment. By using the tool's tutorials, design wizards, and user-friendly data entry screens, engineers can now create complete, robust timing solutions in minutes. And because ADIsimCLK models the phase noise and jitter of the components used, final system performance can be predicted with great accuracy, allowing designers to move from simulations to final board layouts faster, removing iterations from the design process and speeding time to market. The new tool is offered as a free download from ADI's website.
ADIsimCLK Simulates Jitter of Less Than 1 Picosecond RMS
Based on ADI's popular ADIsimPLLTM tool for low-phase-noise PLL synthesizer design, ADIsimCLK is the first tool of its kind to simulate jitter of less than 1 picosecond rms and phase noise less than -150 dBc/Hz. ADIsimCLK simplifies loop filter design and optimization and enables customers to test the functionality and performance of Analog Devices' family of low jitter clock ICs without touching any hardware.
The tool features a data panel that allows designers to alter loop bandwidths, change charge pump currents, set divide ratios, adjust delays, and choose output drivers. The tool's result panel displays overall frequency response, timing diagrams, schematics, and provides detailed performance data on each individual clock output. Equipped with a library of references, VCOs and VCXOs, ADIsimCLK allows the designer to observe exactly how each component affects the clock distribution design at the touch of a button.
