Datasheet ADL5502 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 450 MHz TO 6000 MHz Crest Factor Detector |
| Pages / Page | 30 / 9 — ADL5502. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. BALL A1. CORNER. … |
| Revision | A |
| File Format / Size | PDF / 1.8 Mb |
| Document Language | English |
ADL5502. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. BALL A1. CORNER. ENBL. FLTR. VRMS. VPOS. PEAK. RFIN. CNTL. COMM. TOP VIEW. (BALL SIDE DOWN)
Text Version of Document
ADL5502 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 CORNER ENBL ADL5502 FLTR 1 8 7 VRMS VPOS 2 6 PEAK 3 4 5 RFIN CNTL COMM
03 0
TOP VIEW
1-
(BALL SIDE DOWN)
63 07 Figure 3. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 FLTR Modulation Filter Pin. Connection for an external capacitor to lower the corner frequency of the modulation filter. 2 VPOS Supply Voltage Pin. Operational range 2.5 V to 3.3 V. 3 RFIN Signal Input Pin. Internally ac-coupled after internal termination resistance. Nominal 500 Ω input impedance. 4 COMM Device Ground Pin. 5 CNTL Control Pin. Connect pin to ground for peak-hold mode. Connect pin to VS for reset mode (tracking envelope). To measure the peak of a waveform, the control pin must be briefly set to high (reset mode for >1 μs) to start at a known state. 6 PEAK Envelope Peak Output. Voltage output for peak-hold function, with limited current drive capability. The output has an internal 100 Ω series resistance. Low capacitance loads are recommended to allow for envelope tracking and fast response time. 7 VRMS RMS Output Pin. Rail-to-rail voltage output with limited current drive capability. The output has an internal 100 Ω series resistance. High resistive loads and low capacitance loads are recommended to preserve output swing and allow fast response. 8 ENBL Enable Pin. Connect pin to VS for normal operation. Connect pin to ground for disable mode. Rev. A | Page 7 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION RMS CIRCUIT DESCRIPTION AND FILTERING FILTERING ENVELOPE PEAK-HOLD CIRCUIT OUTPUT BUFFERS MEASURING THE CREST FACTOR APPLICATIONS INFORMATION BASIC CONNECTIONS RF INPUT INTERFACING Resistive Tap RF Input Multiple RF Inputs LINEARITY Output Swing VRMS Output Offset OUTPUT DRIVE CAPABILITY AND BUFFERING SELECTING THE SQUARE-DOMAIN FILTER AND OUTPUT LOW-PASS FILTER POWER CONSUMPTION, ENABLE, AND POWER-ON/POWER-OFF RESPONSE TIME DEVICE CALIBRATION AND ERROR CALCULATION CALIBRATION FOR IMPROVED ACCURACY CALCULATION OF CREST FACTOR (CF) DRIFT OVER A REDUCED TEMPERATURE RANGE OPERATION AT HIGH FREQUENCIES DEVICE HANDLING EVALUATION BOARD Operating in Peak-Hold Mode Land Pattern and Soldering Information OUTLINE DIMENSIONS ORDERING GUIDE
03 0
TOP VIEW
1-
(BALL SIDE DOWN)
63 07 Figure 3. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 FLTR Modulation Filter Pin. Connection for an external capacitor to lower the corner frequency of the modulation filter. 2 VPOS Supply Voltage Pin. Operational range 2.5 V to 3.3 V. 3 RFIN Signal Input Pin. Internally ac-coupled after internal termination resistance. Nominal 500 Ω input impedance. 4 COMM Device Ground Pin. 5 CNTL Control Pin. Connect pin to ground for peak-hold mode. Connect pin to VS for reset mode (tracking envelope). To measure the peak of a waveform, the control pin must be briefly set to high (reset mode for >1 μs) to start at a known state. 6 PEAK Envelope Peak Output. Voltage output for peak-hold function, with limited current drive capability. The output has an internal 100 Ω series resistance. Low capacitance loads are recommended to allow for envelope tracking and fast response time. 7 VRMS RMS Output Pin. Rail-to-rail voltage output with limited current drive capability. The output has an internal 100 Ω series resistance. High resistive loads and low capacitance loads are recommended to preserve output swing and allow fast response. 8 ENBL Enable Pin. Connect pin to VS for normal operation. Connect pin to ground for disable mode. Rev. A | Page 7 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION RMS CIRCUIT DESCRIPTION AND FILTERING FILTERING ENVELOPE PEAK-HOLD CIRCUIT OUTPUT BUFFERS MEASURING THE CREST FACTOR APPLICATIONS INFORMATION BASIC CONNECTIONS RF INPUT INTERFACING Resistive Tap RF Input Multiple RF Inputs LINEARITY Output Swing VRMS Output Offset OUTPUT DRIVE CAPABILITY AND BUFFERING SELECTING THE SQUARE-DOMAIN FILTER AND OUTPUT LOW-PASS FILTER POWER CONSUMPTION, ENABLE, AND POWER-ON/POWER-OFF RESPONSE TIME DEVICE CALIBRATION AND ERROR CALCULATION CALIBRATION FOR IMPROVED ACCURACY CALCULATION OF CREST FACTOR (CF) DRIFT OVER A REDUCED TEMPERATURE RANGE OPERATION AT HIGH FREQUENCIES DEVICE HANDLING EVALUATION BOARD Operating in Peak-Hold Mode Land Pattern and Soldering Information OUTLINE DIMENSIONS ORDERING GUIDE
