Datasheet LT1355, LT1356 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual and Quad 12MHz, 400V/µs Op Amps |
| Pages / Page | 16 / 10 — APPLICATIONS INFORMATION. Layout and Passive Components. The part should … |
| File Format / Size | PDF / 692 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Layout and Passive Components. The part should not be used as a
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LT1355/LT1356
APPLICATIONS INFORMATION Layout and Passive Components
The inputs can withstand transient differential input volt- The LT1355/LT1356 amplifiers are easy to use and tolerant ages up to 10V without damage and need no clamping of less than ideal layouts. For maximum performance (for or source resistance for protection. Differential inputs, example, fast 0.01% settling) use a ground plane, short however, generate large supply currents (tens of mA) as lead lengths, and RF-quality bypass capacitors (0.01µF to required for high slew rates. If the device is used with 0.1µF). For high drive current applications use low ESR sustained differential inputs, the average supply current will bypass capacitors (1µF to 10µF tantalum). increase, excessive power dissipation will result and the part may be damaged.
The part should not be used as a
The parallel combination of the feedback resistor and gain
comparator, peak detector or other open-loop application
setting resistor on the inverting input combine with the
with large, sustained differential inputs.
Under normal, input capacitance to form a pole which can cause peaking closed-loop operation, an increase of power dissipation is or oscillations. If feedback resistors greater than 5k are only noticeable in applications with large slewing outputs used, a parallel capacitor of value: and is proportional to the magnitude of the differential input C voltage and the percent of the time that the inputs are apart. F > RG x CIN/RF Measure the average supply current for the application in should be used to cancel the input pole and optimize order to calculate the power dissipation. dynamic performance. For unity-gain applications where a large feedback resistor is used, CF should be greater
Circuit Operation
than or equal to CIN. The LT1355/LT1356 circuit topology is a true voltage
Capacitive Loading
feedback amplifier that has the slewing behavior of a cur- rent feedback amplifier. The operation of the circuit can The LT1355/LT1356 are stable with any capacitive load. be understood by referring to the simplified schematic. As the capacitive load increases, both the bandwidth and The inputs are buffered by complementary NPN and phase margin decrease so there will be peaking in the PNP emitter followers which drive an 800Ω resistor. frequency domain and in the transient response. Coaxial The input voltage appears across the resistor generating cable can be driven directly, but for best pulse fidelity a currents which are mirrored into the high impedance resistor of value equal to the characteristic impedance of node. Complementary followers form an output stage the cable (i.e., 75Ω) should be placed in series with the which buffers the gain node from the load. The bandwidth output. The other end of the cable should be terminated is set by the input resistor and the capacitance on the with the same value resistor to ground. high impedance node. The slew rate is determined by the
Input Considerations
current available to charge the gain node capacitance. This current is the differential input voltage divided by Each of the LT1355/LT1356 inputs is the base of an NPN R1, so the slew rate is proportional to the input. Highest and a PNP transistor whose base currents are of opposite slew rates are therefore seen in the lowest gain configura- polarity and provide first-order bias current cancellation. tions. For example, a 10V output step in a gain of 10 has Because of variation in the matching of NPN and PNP beta, only a 1V input step, whereas the same output step in the polarity of the input bias current can be positive or unity gain has a 10 times greater input step. The curve of negative. The offset current does not depend on NPN/PNP Slew Rate vs Input Level illustrates this relationship. The beta matching and is well controlled. The use of balanced LT1355/LT1356 are tested for slew rate in a gain of –2 so source resistance at each input is recommended for ap- higher slew rates can be expected in gains of 1 and –1, plications where DC accuracy must be maximized. and lower slew rates in higher gain configurations. 13556fc 10 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Applications Information Simplified Schematic Package Description Revision History Typical Applications Related Parts
APPLICATIONS INFORMATION Layout and Passive Components
The inputs can withstand transient differential input volt- The LT1355/LT1356 amplifiers are easy to use and tolerant ages up to 10V without damage and need no clamping of less than ideal layouts. For maximum performance (for or source resistance for protection. Differential inputs, example, fast 0.01% settling) use a ground plane, short however, generate large supply currents (tens of mA) as lead lengths, and RF-quality bypass capacitors (0.01µF to required for high slew rates. If the device is used with 0.1µF). For high drive current applications use low ESR sustained differential inputs, the average supply current will bypass capacitors (1µF to 10µF tantalum). increase, excessive power dissipation will result and the part may be damaged.
The part should not be used as a
The parallel combination of the feedback resistor and gain
comparator, peak detector or other open-loop application
setting resistor on the inverting input combine with the
with large, sustained differential inputs.
Under normal, input capacitance to form a pole which can cause peaking closed-loop operation, an increase of power dissipation is or oscillations. If feedback resistors greater than 5k are only noticeable in applications with large slewing outputs used, a parallel capacitor of value: and is proportional to the magnitude of the differential input C voltage and the percent of the time that the inputs are apart. F > RG x CIN/RF Measure the average supply current for the application in should be used to cancel the input pole and optimize order to calculate the power dissipation. dynamic performance. For unity-gain applications where a large feedback resistor is used, CF should be greater
Circuit Operation
than or equal to CIN. The LT1355/LT1356 circuit topology is a true voltage
Capacitive Loading
feedback amplifier that has the slewing behavior of a cur- rent feedback amplifier. The operation of the circuit can The LT1355/LT1356 are stable with any capacitive load. be understood by referring to the simplified schematic. As the capacitive load increases, both the bandwidth and The inputs are buffered by complementary NPN and phase margin decrease so there will be peaking in the PNP emitter followers which drive an 800Ω resistor. frequency domain and in the transient response. Coaxial The input voltage appears across the resistor generating cable can be driven directly, but for best pulse fidelity a currents which are mirrored into the high impedance resistor of value equal to the characteristic impedance of node. Complementary followers form an output stage the cable (i.e., 75Ω) should be placed in series with the which buffers the gain node from the load. The bandwidth output. The other end of the cable should be terminated is set by the input resistor and the capacitance on the with the same value resistor to ground. high impedance node. The slew rate is determined by the
Input Considerations
current available to charge the gain node capacitance. This current is the differential input voltage divided by Each of the LT1355/LT1356 inputs is the base of an NPN R1, so the slew rate is proportional to the input. Highest and a PNP transistor whose base currents are of opposite slew rates are therefore seen in the lowest gain configura- polarity and provide first-order bias current cancellation. tions. For example, a 10V output step in a gain of 10 has Because of variation in the matching of NPN and PNP beta, only a 1V input step, whereas the same output step in the polarity of the input bias current can be positive or unity gain has a 10 times greater input step. The curve of negative. The offset current does not depend on NPN/PNP Slew Rate vs Input Level illustrates this relationship. The beta matching and is well controlled. The use of balanced LT1355/LT1356 are tested for slew rate in a gain of –2 so source resistance at each input is recommended for ap- higher slew rates can be expected in gains of 1 and –1, plications where DC accuracy must be maximized. and lower slew rates in higher gain configurations. 13556fc 10 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Applications Information Simplified Schematic Package Description Revision History Typical Applications Related Parts
