Datasheet AD9430 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 12-Bit, 170/210 MSPS 3.3 V A/D Converter |
| Pages / Page | 45 / 8 — AD9430. DIGITAL SPECIFICATIONS. Table 3. Test. AD9430-170. AD9430-210. … |
| Revision | E |
| File Format / Size | PDF / 1.5 Mb |
| Document Language | English |
AD9430. DIGITAL SPECIFICATIONS. Table 3. Test. AD9430-170. AD9430-210. Parameter. Temp. Level. Min. Typ. Max. Unit
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AD9430 DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 3. Test AD9430-170 AD9430-210 Parameter Temp Level Min Typ Max Min Typ Max Unit
ENCODE AND DS INPUTS (CLK+, CLK–, DS+, DS–)1 Differential Input Voltage2 Full IV 0.2 0.2 V Common-Mode Voltage3 Full VI 1.375 1.5 1.575 1.375 1.5 1.575 V Input Resistance Full VI 3.2 5.5 6.5 3.2 5.5 6.5 kΩ Input Capacitance 25°C V 4 4 pF LOGIC INPUTS (S1, S2, S4, S5) Logic 1 Voltage Full IV 2.0 2.0 V Logic 0 Voltage Full IV 0.8 0.8 V Logic 1 Input Current Full VI 190 190 μA Logic 0 Input Current Full VI 10 10 μA Input Resistance 25°C V 30 30 kΩ Input Capacitance 25°C V 4 4 pF LOGIC OUTPUTS (CMOS Mode) Logic 1 Voltage4 Full IV DRVDD DRVDD V –0.05 –0.05 Logic 0 Voltage4 Full IV 0.05 0.05 V LOGIC OUTPUTS (LVDS Mode)4, 5 VOD Differential Output Voltage Full VI 247 454 247 454 mV VOS Output Offset Voltage Full VI 1.125 1.375 1.125 1.375 V Output Coding Twos complement or binary Twos complement or binary 1 ENCODE (Clock) and DS inputs identical on the chip. See the Equivalent Circuits section. 2 All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV. 3 ENCODE (Clock) inputs’ common-mode can be externally set, such that 0.9 V < (CLK+ or CLK−) < 2.6 V. 4 Digital output logic levels: DRVDD = 3.3 V, CLOAD = 5 pF. 5 LVDS RTERM = 100 Ω, LVDS output current set resistor (RSET) = 3.74 kΩ (1% tolerance). Rev. E | Page 7 of 44 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION APPLICATIONS TABLE OF CONTENTS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY APPLICATION NOTES THEORY OF OPERATION ENCODE INPUT ANALOG INPUT DS INPUTS (DS+, DS–) CMOS OUTPUTS LVDS OUTPUTS VOLTAGE REFERENCE NOISE POWER RATIO TESTING (NPR) EVALUATION BOARD, CMOS MODE POWER CONNECTOR ANALOG INPUTS GAIN ENCODE VOLTAGE REFERENCE DATA FORMAT SELECT I/P TIMING SELECT TIMING CONTROLS CMOS DATA OUTPUTS CRYSTAL OSCILLATOR OPTIONAL AMPLIFIER TROUBLESHOOTING EVALUATION BOARD, LVDS MODE POWER CONNECTOR ANALOG INPUTS GAIN CLOCK VOLTAGE REFERENCE DATA FORMAT SELECT DATA OUTPUTS CRYSTAL OSCILLATOR OUTLINE DIMENSIONS ORDERING GUIDE
AD9430 DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 3. Test AD9430-170 AD9430-210 Parameter Temp Level Min Typ Max Min Typ Max Unit
ENCODE AND DS INPUTS (CLK+, CLK–, DS+, DS–)1 Differential Input Voltage2 Full IV 0.2 0.2 V Common-Mode Voltage3 Full VI 1.375 1.5 1.575 1.375 1.5 1.575 V Input Resistance Full VI 3.2 5.5 6.5 3.2 5.5 6.5 kΩ Input Capacitance 25°C V 4 4 pF LOGIC INPUTS (S1, S2, S4, S5) Logic 1 Voltage Full IV 2.0 2.0 V Logic 0 Voltage Full IV 0.8 0.8 V Logic 1 Input Current Full VI 190 190 μA Logic 0 Input Current Full VI 10 10 μA Input Resistance 25°C V 30 30 kΩ Input Capacitance 25°C V 4 4 pF LOGIC OUTPUTS (CMOS Mode) Logic 1 Voltage4 Full IV DRVDD DRVDD V –0.05 –0.05 Logic 0 Voltage4 Full IV 0.05 0.05 V LOGIC OUTPUTS (LVDS Mode)4, 5 VOD Differential Output Voltage Full VI 247 454 247 454 mV VOS Output Offset Voltage Full VI 1.125 1.375 1.125 1.375 V Output Coding Twos complement or binary Twos complement or binary 1 ENCODE (Clock) and DS inputs identical on the chip. See the Equivalent Circuits section. 2 All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV. 3 ENCODE (Clock) inputs’ common-mode can be externally set, such that 0.9 V < (CLK+ or CLK−) < 2.6 V. 4 Digital output logic levels: DRVDD = 3.3 V, CLOAD = 5 pF. 5 LVDS RTERM = 100 Ω, LVDS output current set resistor (RSET) = 3.74 kΩ (1% tolerance). Rev. E | Page 7 of 44 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION APPLICATIONS TABLE OF CONTENTS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY APPLICATION NOTES THEORY OF OPERATION ENCODE INPUT ANALOG INPUT DS INPUTS (DS+, DS–) CMOS OUTPUTS LVDS OUTPUTS VOLTAGE REFERENCE NOISE POWER RATIO TESTING (NPR) EVALUATION BOARD, CMOS MODE POWER CONNECTOR ANALOG INPUTS GAIN ENCODE VOLTAGE REFERENCE DATA FORMAT SELECT I/P TIMING SELECT TIMING CONTROLS CMOS DATA OUTPUTS CRYSTAL OSCILLATOR OPTIONAL AMPLIFIER TROUBLESHOOTING EVALUATION BOARD, LVDS MODE POWER CONNECTOR ANALOG INPUTS GAIN CLOCK VOLTAGE REFERENCE DATA FORMAT SELECT DATA OUTPUTS CRYSTAL OSCILLATOR OUTLINE DIMENSIONS ORDERING GUIDE
