Datasheet ADXL356, ADXL357 (Analog Devices) - 7

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Data Sheet ADXL356/ADXL357 I2C DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL357
Note that multifunction pin names may be referenced only by their relevant function.
Table 4. Test Conditions/ I2C_HS = 0 (Fast Mode) I2C_HS = 1 (High Speed Mode) Parameter Symbol Comments Min Typ Max Min Typ Max Unit
DC INPUT LEVELS Input Voltage Low Level V 0.3 × V 0.3 × V V IL DDIO DDIO High Level V 0.7 × V 0.7 × V V IH DDIO DDIO Hysteresis of Schmitt V 0.05 × V 0.1 × V µA HYS DDIO DDIO Triggered Inputs Input Current I 0.1 × V < V < −10 +10 µA IL DDIO IN 0.9 × V DDIO DC OUTPUT LEVELS Output Voltage I = 3 mA OL Low Level V V > 2 V 0.4 V OL1 DDIO V V ≤ 2 V 0.2 × V V OL2 DDIO DDIO Output Current Low Level I V = 0.4 V 20 mA OL OL V = 0.6 V 6 mA OL AC INPUT LEVELS SCL Frequency 0 1 0 3.4 MHz SCL High Time t 260 60 ns HIGH SCL Low Time t 500 160 ns LOW Start Setup Time t 260 160 ns SUSTA Start Hold Time t 260 160 ns HDSTA SDA Setup Time t 50 10 ns SUDAT SDA Hold Time t 0 0 ns HDDAT Stop Setup Time t 260 160 ns SUSTO Bus Free Time t 500 ns BUF SCL Input Rise Time t 120 80 ns RCL SCL Input Fall Time t 120 80 ns FCL SDA Input Rise Time t 120 160 ns RDA SDA Input Fall Time t 120 160 ns FDA Width of Spikes to t Not shown in Figure 4 50 10 ns SP Suppress AC OUTPUT LEVELS Propagation Delay C = 500 pF LOAD Data t 97 450 27 135 ns VDDAT Acknowledge t 450 ns VDACK Output Fall Time t Not shown in Figure 4 20 × 120 ns F (V /5.5) DDIO
t t FDA tRDA BUF SDA t t tVDDAT t t HDSTA SUSTA VDACK tSUSTO SUSTA tSUDAT tHDDAT tLOW t t HIGH FCL tRCL tVDDAT
004
SCL
15429- Figure 4. I2C Interface Timing Diagram Rev. 0 | Page 7 of 42 Document Outline Features Applications Functional Block Diagrams General Description Revision History Specifications Analog Output for the ADXL356 Digital Output for the ADXL357 SPI Digital Interface Characteristics for the ADXL357 I2C Digital Interface Characteristics for the ADXL357 Absolute Maximum Ratings Thermal Resistance Recommended Soldering Profile ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Root Allan Variance (RAV) ADXL357 Characteristics Theory of Operation Applications Information Analog Output Digital Output Axes of Acceleration Sensitivity Power Sequencing Power Supply Description VSUPPLY V1P8ANA V1P8DIG VDDIO Overrange Protection Self Test Filter Serial Communications SPI Protocol I2C Protocol Reading Acceleration or Temperature Data from the Interface FIFO Interrupts DATA_RDY DRDY Pin FIFO_FULL FIFO_OVR Activity NVM_BUSY External Synchronization and Interpolation EXT_SYNC = 00—No External Sync or Interpolation EXT_SYNC = 10—External Sync with Interpolation EXT_SYNC = 01—External Sync and External Clock, No Interpolation Filter ADXL357 Register Map Register Definitions Analog Devices ID Register Address: 0x00, Reset: 0xAD, Name: DEVID_AD Analog Devices MEMS ID Register Address: 0x01, Reset: 0x1D, Name: DEVID_MST Device ID Register Address: 0x02, Reset: 0xED, Name: PARTID Product Revision ID Register Address: 0x03, Reset: 0x01, Name: REVID Status Register Address: 0x04, Reset: 0x00, Name: Status FIFO Entries Register Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES Temperature Data Registers Address: 0x06, Reset: 0x00, Name: TEMP2 Address: 0x07, Reset: 0x00, Name: TEMP1 X-Axis Data Registers Address: 0x08, Reset: 0x00, Name: XDATA3 Address: 0x09, Reset: 0x00, Name: XDATA2 Address: 0x0A, Reset: 0x00, Name: XDATA1 Y-Axis Data Registers Address: 0x0B, Reset: 0x00, Name: YDATA3 Address: 0x0C, Reset: 0x00, Name: YDATA2 Address: 0x0D, Reset: 0x00, Name: YDATA1 Z-Axis Data Registers Address: 0x0E, Reset: 0x00, Name: ZDATA3 Address: 0x0F, Reset: 0x00, Name: ZDATA2 Address: 0x10, Reset: 0x00, Name: ZDATA1 FIFO Access Register Address: 0x11, Reset: 0x00, Name: FIFO_DATA X-Axis Offset Trim Registers Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L Y-Axis Offset Trim Registers Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L Z-Axis Offset Trim Registers Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L Activity Enable Register Address: 0x24, Reset: 0x00, Name: ACT_EN Activity Threshold Registers Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L Activity Count Register Address: 0x27, Reset: 0x01, Name: ACT_COUNT Filter Settings Register Address: 0x28, Reset: 0x00, Name: Filter FIFO Samples Register Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES Interrupt Pin (INTx) Function Map Register Address: 0x2A, Reset: 0x00, Name: INT_MAP Data Synchronization Address: 0x2B, Reset: 0x00, Name: Sync I2C Speed, Interrupt Polarity, and Range Register Address: 0x2C, Reset: 0x81, Name: Range Power Control Register Address: 0x2D, Reset: 0x01, Name: POWER_CTL Self Test Register Address: 0x2E, Reset: 0x00, Name: SELF_TEST Reset Register Address: 0x2F, Reset: 0x00, Name: Reset PCB Footprint Pattern Outline Dimensions Ordering Guide