Datasheet ADIS16201 (Analog Devices) - 6

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Data Sheet ADIS16201 TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.
Table 2. Parameter Description Min1 Ty p Max Unit
fSCLK Fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz) 0.01 2.5 MHz Normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz) 0.01 1.0 MHz tDATARATE Chip select period, fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz) 32 μs tDATARATE Chip select period, normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz) 42 μs tSTALL Stall period, fast mode, SMPL_PRD ≤ 0x07 (fs ≥ 1024 Hz) 10 μs tSTALL Stall period, normal mode, SMPL_PRD ≥ 0x08 (fs ≤ 910 Hz) 12 μs tcs Chip select to clock edge 48.8 ns tDAV Data output valid after SCLK edge 100 ns tDSU Data input setup time before SCLK rising edge 24.4 ns tDHD Data input hold time after SCLK rising edge 48.8 ns tDF Data output fall time 5 12.5 ns min tDR Data output rise time 5 12.5 ns min tSFS CS high after SCLK edge 5 ns typ 1 Guaranteed by design, not tested.
TIMING DIAGRAMS tDATA RATE tSTALL CS SCLK
2 00 2-
t
46
STALL = tDATA RATE – 16/fSCLK
05

Figure 2. SPI Chip Select Timing
CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN W/R A5 A4 A3 A2 D2 D1 LSB
03 0 2- 46 05 Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1) Rev. C | Page 5 of 32 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Accelerometer Operation Inclinometer Operation Temperature Sensor Basic Operation Data Output Register Access Programming and Control Control Register Overview Control Register Access Control Register Details Calibration Calibration Register Definitions XACCL_OFF Register Definition XACCL_SCALE Register Definition YACCL_OFF Register Definition YACCL_SCALE Register Definition XINCL_OFF Register Definition XINCL_SCALE Register Definition YINCL_OFF Register Definition YINCL_SCALE Register Definition Alarms ALM_MAG1 Register Definition ALM_SMPL1 Register Definition ALM_MAG2 Register Definition ALM_SMPL2 Register Definition ALM_CTRL Register Definition Sample Period Control SMPL_PRD Register Definition Filtering Control AVG_CNT Register Definition Power-Down Control PWR_MDE Register Definition Status Feedback STATUS Register Definition Command Control COMMAND Register Definition Miscellaneous Control Register MSC_CTRL Register Definition Peripherals Auxiliary ADC Function Auxiliary DAC Function AUX_DAC Register Definition General Purpose I/O Control GPIO_CTRL Register Definition Applications Serial Peripheral Interface (SPI) Hardware Considerations Grounding and Board Layout Recomendations Bandgap Reference Power-On Reset Operation Second-Level Assembly Example Pad Layout Outline Dimensions Ordering Guide