Datasheet ATmega103, ATmega103L (Atmel) - 8

Architectural Figure 4.
The ATmega103(L) AVR RISC Architecture
Overview
AVR ATmega103(L) Architecture Data Bus 8-bit 64K x 16 Program Status Program Counter and Test Memory 32 x 8 Instruction General Register Purpose Registers Instruction Peripherals Decoder ALU Control Lines Direct Addressing Indirect Addressing 4K x 8 Data SRAM 4K x 8 EEPROM The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The Program memory is accessed with a single-level pipeline. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Programmable Flash memory. With a few exceptions, AVR instructions have a single 16-bit word format, meaning that every Program memory address contains a single 16-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM and, consequently, the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 16-bit Stack Pointer (SP) is read/write accessible in the I/O space. The 4000 bytes data SRAM can be easily accessed through the five different address- ing modes supported in the AVR architecture. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All the different interrupts have a sep-
8 ATmega103(L)
0945I–AVR–02/07 Document Outline Features Pin Configuration Description Block Diagram Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E (PE7..PE0) Port F (PF7..PF0) RESET XTAL1 XTAL2 TOSC1 TOSC2 WR RD ALE AVCC AREF AGND PEN Clock Options Crystal Oscillator External Clock Timer Oscillator Architectural Overview General Purpose Register File X-register, Y-register and Z- register ALU - Arithmetic Logic Unit ISP Flash Program Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post- increment Constant Addressing Using the LPM and ELPM Instructions Direct Program Address, JMP and CALL Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing I/O Memory Status Register - SREG Stack Pointer - SP RAM Page Z Select Register - RAMPZ MCU Control Register - MCUCR XTAL Divide Control Register - XDIV Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Watchdog Reset MCU Status Register - MCUSR Interrupt Handling External Interrupt Mask Register - EIMSK External Interrupt Flag Register - EIFR External Interrupt Control Register - EICR Timer/Counter Interrupt Mask Register - TIMSK Timer/Counter Interrupt Flag Register - TIFR Interrupt Response Time Sleep Modes Idle Mode Power-down Mode Power-save Mode Timer/Counters Timer/Counter Prescalers 8-bit Timer/Counters T/C0 and T/C2 Timer/Counter0 Control Register - TCCR0 Timer/Counter2 Control Register - TCCR2 Timer/Counter0 - TCNT0 Timer/Counter2 - TCNT2 Timer/Counter0 Output Compare Register - OCR0 Timer/Counter2 Output Compare Register - OCR2 Timer/Counters 0 and 2 in PWM Mode Asynchronous Status Register - ASSR Asynchronous Operation of Timer/Counter0 16-bit Timer/Counter1 Timer/Counter1 Control Register A - TCCR1A Timer/Counter1 Control Register B - TCCR1B Timer/Counter1 - TCNT1H and TCNT1L Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL Timer/Counter1 Input Capture Register - ICR1H and ICR1L Timer/Counter1 in PWM Mode Watchdog Timer Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access EEPROM Address Register - EEARH, EEARL EEPROM Data Register - EEDR EEPROM Control Register - EECR Prevent EEPROM Corruption Serial Peripheral Interface - SPI SS Pin Functionality Data Modes SPI Control Register - SPCR SPI Status Register - SPSR SPI Data Register - SPDR UART Data Transmission Data Reception UART Control UART I/O Data Register - UDR UART Status Register - USR UART Control Register - UCR Baud Rate Generator UART Baud Rate Register - UBRR Analog Comparator Analog Comparator Control and Status Register - ACSR Analog-to-Digital Converter Feature list: Operation Prescaling ADC Noise Canceler Function ADC Multiplexer Select Register - ADMUX ADC Control and Status Register - ADCSR ADC Data Register - ADCL and ADCH ADC Noise Canceling Techniques ADC DC Characteristics Interface to External SRAM I/O Ports Port A Port A Data Register - PORTA Port A Data Direction Register - DDRA Port A Input Pins Address - PINA Port A as General Digital I/O Port A Schematics Port B Port B Data Register - PORTB Port B Data Direction Register - DDRB Port B Input Pins Address - PINB Port B as General Digital I/O Alternate Functions of Port B Port B Schematics Port C The Port C Data Register - PORTC Port C Schematics Port D Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Port D as General Digital I/O Alternate Functions of Port D Port D Schematics Port E Port E Data Register - PORTE Port E Data Direction Register - DDRE Port E Input Pins Address - PINE Port E as General Digital I/O Alternate Functions of Port E Port E Schematics Port F Port F Input Pins Address - PINF Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling for the EEPROM Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Data Memory Timing External Clock Drive Waveforms Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 64A Table of Contents