Datasheet ATmega103, ATmega103L (Atmel) - 9
| Manufacturer | Atmel |
| Description | 8-bit AVR Microcontroller with 128K Bytes In-System Programmable Flash |
| Pages / Page | 141 / 9 — ATmega103(L). General Purpose. Register File. Figure 5 |
| File Format / Size | PDF / 2.2 Mb |
| Document Language | English |
ATmega103(L). General Purpose. Register File. Figure 5
Model Line for this Datasheet
Text Version of Document
link to page 9 link to page 9
ATmega103(L)
arate Interrupt Vector in the Interrupt Vector table at the beginning of the Program memory. The different interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The memory spaces in the AVR architecture are all linear and regular memory maps.
General Purpose
Figure 5 shows the structure of the 32 general purpose working registers in the CPU.
Register File Figure 5.
AVR CPU General Purpose Working Registers 7 0 Addr. R0 $00 R1 $01 R2 $02 . R13 $0D General R14 $0E Purpose R15 $0F Working R16 $10 Registers R17 $11 . R26 $1A X-register Low Byte R27 $1B X-register High Byte R28 $1C Y-register Low Byte R29 $1D Y-register High Byte R30 $1E Z-register Low Byte R31 $1F Z-register High Byte All the register operating instructions in the instruction set have direct and single-cycle access to all registers. The only exception are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the Register File – R16..R31. The general SBC, SUB, CP, AND and OR and all other operations between two registers or on a single register apply to the entire Register File. As shown in Figure 5, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being phys- ically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any register in the file. The 4K bytes of SRAM available for general data are implemented as addresses $0060 to $0FFF.
9
0945I–AVR–02/07 Document Outline Features Pin Configuration Description Block Diagram Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E (PE7..PE0) Port F (PF7..PF0) RESET XTAL1 XTAL2 TOSC1 TOSC2 WR RD ALE AVCC AREF AGND PEN Clock Options Crystal Oscillator External Clock Timer Oscillator Architectural Overview General Purpose Register File X-register, Y-register and Z- register ALU - Arithmetic Logic Unit ISP Flash Program Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post- increment Constant Addressing Using the LPM and ELPM Instructions Direct Program Address, JMP and CALL Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing I/O Memory Status Register - SREG Stack Pointer - SP RAM Page Z Select Register - RAMPZ MCU Control Register - MCUCR XTAL Divide Control Register - XDIV Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Watchdog Reset MCU Status Register - MCUSR Interrupt Handling External Interrupt Mask Register - EIMSK External Interrupt Flag Register - EIFR External Interrupt Control Register - EICR Timer/Counter Interrupt Mask Register - TIMSK Timer/Counter Interrupt Flag Register - TIFR Interrupt Response Time Sleep Modes Idle Mode Power-down Mode Power-save Mode Timer/Counters Timer/Counter Prescalers 8-bit Timer/Counters T/C0 and T/C2 Timer/Counter0 Control Register - TCCR0 Timer/Counter2 Control Register - TCCR2 Timer/Counter0 - TCNT0 Timer/Counter2 - TCNT2 Timer/Counter0 Output Compare Register - OCR0 Timer/Counter2 Output Compare Register - OCR2 Timer/Counters 0 and 2 in PWM Mode Asynchronous Status Register - ASSR Asynchronous Operation of Timer/Counter0 16-bit Timer/Counter1 Timer/Counter1 Control Register A - TCCR1A Timer/Counter1 Control Register B - TCCR1B Timer/Counter1 - TCNT1H and TCNT1L Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL Timer/Counter1 Input Capture Register - ICR1H and ICR1L Timer/Counter1 in PWM Mode Watchdog Timer Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access EEPROM Address Register - EEARH, EEARL EEPROM Data Register - EEDR EEPROM Control Register - EECR Prevent EEPROM Corruption Serial Peripheral Interface - SPI SS Pin Functionality Data Modes SPI Control Register - SPCR SPI Status Register - SPSR SPI Data Register - SPDR UART Data Transmission Data Reception UART Control UART I/O Data Register - UDR UART Status Register - USR UART Control Register - UCR Baud Rate Generator UART Baud Rate Register - UBRR Analog Comparator Analog Comparator Control and Status Register - ACSR Analog-to-Digital Converter Feature list: Operation Prescaling ADC Noise Canceler Function ADC Multiplexer Select Register - ADMUX ADC Control and Status Register - ADCSR ADC Data Register - ADCL and ADCH ADC Noise Canceling Techniques ADC DC Characteristics Interface to External SRAM I/O Ports Port A Port A Data Register - PORTA Port A Data Direction Register - DDRA Port A Input Pins Address - PINA Port A as General Digital I/O Port A Schematics Port B Port B Data Register - PORTB Port B Data Direction Register - DDRB Port B Input Pins Address - PINB Port B as General Digital I/O Alternate Functions of Port B Port B Schematics Port C The Port C Data Register - PORTC Port C Schematics Port D Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Port D as General Digital I/O Alternate Functions of Port D Port D Schematics Port E Port E Data Register - PORTE Port E Data Direction Register - DDRE Port E Input Pins Address - PINE Port E as General Digital I/O Alternate Functions of Port E Port E Schematics Port F Port F Input Pins Address - PINF Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling for the EEPROM Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Data Memory Timing External Clock Drive Waveforms Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 64A Table of Contents
ATmega103(L)
arate Interrupt Vector in the Interrupt Vector table at the beginning of the Program memory. The different interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The memory spaces in the AVR architecture are all linear and regular memory maps.
General Purpose
Figure 5 shows the structure of the 32 general purpose working registers in the CPU.
Register File Figure 5.
AVR CPU General Purpose Working Registers 7 0 Addr. R0 $00 R1 $01 R2 $02 . R13 $0D General R14 $0E Purpose R15 $0F Working R16 $10 Registers R17 $11 . R26 $1A X-register Low Byte R27 $1B X-register High Byte R28 $1C Y-register Low Byte R29 $1D Y-register High Byte R30 $1E Z-register Low Byte R31 $1F Z-register High Byte All the register operating instructions in the instruction set have direct and single-cycle access to all registers. The only exception are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the Register File – R16..R31. The general SBC, SUB, CP, AND and OR and all other operations between two registers or on a single register apply to the entire Register File. As shown in Figure 5, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being phys- ically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any register in the file. The 4K bytes of SRAM available for general data are implemented as addresses $0060 to $0FFF.
9
0945I–AVR–02/07 Document Outline Features Pin Configuration Description Block Diagram Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E (PE7..PE0) Port F (PF7..PF0) RESET XTAL1 XTAL2 TOSC1 TOSC2 WR RD ALE AVCC AREF AGND PEN Clock Options Crystal Oscillator External Clock Timer Oscillator Architectural Overview General Purpose Register File X-register, Y-register and Z- register ALU - Arithmetic Logic Unit ISP Flash Program Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post- increment Constant Addressing Using the LPM and ELPM Instructions Direct Program Address, JMP and CALL Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing I/O Memory Status Register - SREG Stack Pointer - SP RAM Page Z Select Register - RAMPZ MCU Control Register - MCUCR XTAL Divide Control Register - XDIV Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Watchdog Reset MCU Status Register - MCUSR Interrupt Handling External Interrupt Mask Register - EIMSK External Interrupt Flag Register - EIFR External Interrupt Control Register - EICR Timer/Counter Interrupt Mask Register - TIMSK Timer/Counter Interrupt Flag Register - TIFR Interrupt Response Time Sleep Modes Idle Mode Power-down Mode Power-save Mode Timer/Counters Timer/Counter Prescalers 8-bit Timer/Counters T/C0 and T/C2 Timer/Counter0 Control Register - TCCR0 Timer/Counter2 Control Register - TCCR2 Timer/Counter0 - TCNT0 Timer/Counter2 - TCNT2 Timer/Counter0 Output Compare Register - OCR0 Timer/Counter2 Output Compare Register - OCR2 Timer/Counters 0 and 2 in PWM Mode Asynchronous Status Register - ASSR Asynchronous Operation of Timer/Counter0 16-bit Timer/Counter1 Timer/Counter1 Control Register A - TCCR1A Timer/Counter1 Control Register B - TCCR1B Timer/Counter1 - TCNT1H and TCNT1L Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL Timer/Counter1 Input Capture Register - ICR1H and ICR1L Timer/Counter1 in PWM Mode Watchdog Timer Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access EEPROM Address Register - EEARH, EEARL EEPROM Data Register - EEDR EEPROM Control Register - EECR Prevent EEPROM Corruption Serial Peripheral Interface - SPI SS Pin Functionality Data Modes SPI Control Register - SPCR SPI Status Register - SPSR SPI Data Register - SPDR UART Data Transmission Data Reception UART Control UART I/O Data Register - UDR UART Status Register - USR UART Control Register - UCR Baud Rate Generator UART Baud Rate Register - UBRR Analog Comparator Analog Comparator Control and Status Register - ACSR Analog-to-Digital Converter Feature list: Operation Prescaling ADC Noise Canceler Function ADC Multiplexer Select Register - ADMUX ADC Control and Status Register - ADCSR ADC Data Register - ADCL and ADCH ADC Noise Canceling Techniques ADC DC Characteristics Interface to External SRAM I/O Ports Port A Port A Data Register - PORTA Port A Data Direction Register - DDRA Port A Input Pins Address - PINA Port A as General Digital I/O Port A Schematics Port B Port B Data Register - PORTB Port B Data Direction Register - DDRB Port B Input Pins Address - PINB Port B as General Digital I/O Alternate Functions of Port B Port B Schematics Port C The Port C Data Register - PORTC Port C Schematics Port D Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Port D as General Digital I/O Alternate Functions of Port D Port D Schematics Port E Port E Data Register - PORTE Port E Data Direction Register - DDRE Port E Input Pins Address - PINE Port E as General Digital I/O Alternate Functions of Port E Port E Schematics Port F Port F Input Pins Address - PINF Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling for the EEPROM Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Data Memory Timing External Clock Drive Waveforms Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 64A Table of Contents
