Datasheet ADRV9026 (Analog Devices) - 115

Data Sheet ADRV9026 SYNTHESIZERS
Write commands follow a 24-bit format. The first bit sets the The ADRV9026 contains four fractional-N PLLs to generate bus direction of the bus transfer. The next 15 bits set the the RF LO for the signal paths and all internal clock sources. address where data is written. The final eight bits are the data This group of PLLs includes two RF PLLs for transmit and being transferred to the specific register address. receive LO generation, an auxiliary PLL that can be used by the Read commands follow a similar format with the exception that observation receivers, and a clock PLL. Each PLL is the first 16 bits are transferred on the SPI_DIO pin, and the final independently control ed with no need for external eight bits are read from the ADRV9026, either on the SPI_DO components to set frequencies. pin in 4-wire mode or on the SPI_DIO pin in 3-wire mode.
RF Synthesizers GPIO_X PINS
The two RF synthesizers use fractional-N PLLs to generate RF LOs The ADRV9026 provides 19 general-purpose input/output for multiple receiver and transmitter channels. The fractional- signals (GPIOs) referenced to VIF that can be configured for N PLL incorporates a four-core internal voltage control ed numerous functions. When configured as outputs, certain pins oscillator (VCO) and loop filter, capable of generating low can provide real-time signal information to the baseband phase noise signals with no external components required. An processor, allowing the baseband processor to determine internal LO multiplexer (mux) enables each PLL to supply LOs receiver performance. A pointer register selects what to any or al receivers and transmitters (for example, LO1 to all information is output to these pins. transmitters, LO2 to all receivers), resulting in maximum Signals used for manual gain mode, calibration flags, state flexibility when configuring the device for TDD operation. The machine status, and various receiver parameters are among LOs on multiple devices can be phase synchronized to support the outputs that can be monitored on the GPIO pins. active antenna systems and beam forming applications. Additional y, certain GPIO pins can be configured as inputs and
Auxiliary Synthesizer
used for various functions, such as setting the receiver gain in The auxiliary synthesizer uses a single core VCO fractional-N real time. PLL to generate the signals necessary to calibrate the device.
AUXILIARY CONVERTERS
The output of this block uses a separate mux system to route
GPIO_ANA_x/AUXDAC_x
LOs for calibrating different functions during initialization. The auxiliary synthesizer can also be used to generate LO The ADRV9026 contains eight analog GPIOs (the GPIO_ANA_x signals for the observation receivers or as an offset LO used in pins) that are multiplexed with eight identical auxiliary DACs the receiver signal chains. (AUXDAC_x). The analog GPIO ports can be used to control other analog devices or receive control inputs referenced to the
Clock Synthesizer
VDDA_1P8 supply. The auxiliary DACs are 12-bit converters The ADRV9026 contains a single core VCO fractional-N PLL capable of supplying up to 10 mA. These outputs are typical y synthesizer that generates all baseband related clock signals and used to supply bias current or variable control voltages for SERDES clocks. This fractional-N PLL is programmed based on other related components with analog control inputs. the data rate and sample rate requirements of the system, which
AUXADC_x
typical y require the system to operate in integer mode. The ADRV9026 contains two auxiliary ADCs with four total For JESD204B configurations with Np = 12 and JESD204C input pins (AUXADC_x). These auxiliary ADCs provide 10-bit configurations, a dedicated PLL included in the SERDES block monotonic outputs with an input voltage range of 0.05 V to generates the SERDES clocks. 0.95 V. When enabled, each auxiliary ADC is free running. An
SPI INTERFACE
application programming interface (API) command latches the The ADRV9026 uses a SPI to communicate with the baseband ADC output value to a register. The ADRV9026 also contains processor. This interface can be configured as a 4-wire interface an ADC that supports a built-in diode-based temperature sensor. with dedicated receive and transmit ports, or the interface can be configured as a 3-wire interface with a bidirectional data communications port. This bus allows the baseband processor to set al device control parameters using a simple address data serial bus protocol. Rev. A | Page 115 of 118 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Transmitters and Receivers Synthesizers, Auxiliary Converters, and Clock References Digital Specifications Power Supply Specifications Current Consumption TDD Operation—Four Receiver Channels Enabled TDD Operation—Four Transmitter and One Observation Receiver Channels Enabled FDD Operation—LO1 and LO2, Four Receiver, Four Transmitter, and One Observation Receiver Channels Enabled Digital Interface and Timing Specifications Absolute Maximum Ratings Junction Temperature Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Band 1800 MHz Band 2600 MHz Band 3800 MHz Band 4800 MHz Band 5700 MHz Band Theory of Operation General Transmitter Receiver Observation Receiver Clock Input Synthesizers RF Synthesizers Auxiliary Synthesizer Clock Synthesizer SPI Interface GPIO_x Pins Auxiliary Converters GPIO_ANA_x/AUXDAC_x AUXADC_x JTAG Boundary Scan Applications Information Power Supply Sequence Data Interface Outline Dimensions Ordering Guide