Datasheet HMC8100LP6JE (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Intermediate Frequency Receiver, 800 MHz to 4000 MHz |
| Pages / Page | 27 / 7 — Data Sheet. HMC8100LP6JE. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. … |
| Revision | B |
| File Format / Size | PDF / 745 Kb |
| Document Language | English |
Data Sheet. HMC8100LP6JE. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. K_P. SEN. DVDD. 30 VDD. AMP2_P. 29 IRM_I_N. AMP2_N. 28 IRM_I_P
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Data Sheet HMC8100LP6JE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS K_P N P _ _ CL Q Q _ K _ _ F T O I L N P M M RE RS SD SD SC SEN LO LO IR IR 40 39 38 37 36 35 34 33 32 31 DVDD 1 30 VDD AMP2_P 2 29 IRM_I_N AMP2_N 3 28 IRM_I_P VCC_FILTER 4 27 VCC_IRM HMC8100 FILTER2P 5 26 VCC_VGA1_BALUN VCC_AMP3 6 TOP VIEW 25 VCC_VGA1 GND1 7 (Not to Scale) 24 FILTER1P VCC_BB 8 23 VCC_AMP1 GND2 9 22 AMP1 VGA_EXT_CAP 10 21 GND 11 12 13 14 15 16 17 18 19 20 T 3 1 T U A IN UT IN _ D U G SSI O 3 R CAP CAP O _ RF _ _ _ _ PD T F F 1 RX_O _I CC_P CC_V U AUX A _R V PD V O _ G A 3 V G _ V PD C _ V C V
2
NOTES
-00
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A LOW
7
IMPEDANCE THERMAL AND ELECTRICAL GROUND PLANE.
86 13 Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 DVDD SPI Digital Power Supply (3.3 V dc). See Figure 52 for the required components. 2 AMPT2_P Second Differential Amplifier Output (Positive). 3 AMP2_N Second Differential Amplifier Output (Negative). 4 VCC_FILTER Power Supply for the Filter (3.3 V dc). See Figure 52 for the required components. 5 FILTER2P Input of the Third External Filter Amplifier. 6 VCC_AMP3 Power Supply for the Third External Filter Amplifier (3.3 V dc). See Figure 52 for the required components. 7, 9, 21 GND1, GND2, GND3 Ground Connect. 8 VCC_BB Power Supply for the Baseband Blocks (3.3 V dc). See Figure 52 for the required components. 10 VGA_EXT_CAP External Capacitor for VGA3. See Figure 52 for the required components. 11 RX_OUT Receiver Output. 12 VCC_VGA3 Power Supply for VGA3 (3.3 V dc). See Figure 52 for the required components. 13 AUX_OUT Receiver Auxiliary Output. 14 PD3_IN Receive AGC Loop Input. 15 PD3_OUT/RSSI Third Power Detector Output. 16 VC_VGA_IF/CAP− Control Voltage of IFVGA/AGC Integrator Capacitor. See Figure 52 for the required components. 17 VC_VGA_RF/CAP+ Control Voltage of RFVGA/AGC Integrator Capacitor. See Figure 52 for the required components. 18 VCC_PD1 Power Supply for the First Power Detector (3.3 V dc). See Figure 52 for the required components. 19 PD1_OUT First Power Detector Output. 20 RFIN Radio Frequency Input. This pin is matched to 50 Ω. 22 AMP1 Single-Ended Output of Amplifier 1 (3.3 V dc). See Figure 52 for the required components. 23 VCC_AMP1 Power Supply for AMP1 (3.3 V dc). See Figure 52 for the required components. 24 FILTER1P RFVGA Input. 25 VCC_VGA1 Power Supply for the RFVGA (3.3 V dc). See Figure 52 for the required components. 26 VCC_VGA1_BALUN Power Supply for RFVGA Balun(3.3 V dc). See Figure 52 for the required components. 27 VCC_IRM Power Supply for the Image Reject Mixer (3.3 V dc). See Figure 52 for the required components. 28 IRM_I_P Positive In-Phase IF Output for the Image Reject Mixer. 29 IRM_I_N Negative In-Phase IF Output for the Image Reject Mixer. 30 VDD Power Supply for Logic Circuitry (3.3 V dc). See Figure 52 for the required components. 31 IRM_Q_P Positive Quadrature IF Output for the Image Reject Mixer. 32 IRM_Q_N Negative Quadrature IF Output for the Image Reject Mixer. 33 LOP Local Oscillator Input (Positive). This pin is ac-coupled and matched to 50 Ω. Rev. B | Page 7 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS: 800 MHz TO 1800 MHz RF FREQUENCY RANGE ELECTRICAL CHARACTERISTICS: 1800 MHz TO 2800 MHz RF FREQUENCY RANGE ELECTRICAL CHARACTERISTICS: 2800 MHz TO 4000 MHz RF FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL AGC CONFIGURATION INTERNAL AGC CONFIGURATION THEORY OF OPERATION REGISTER ARRAY ASSIGNMENTS AND SERIAL INTERFACE Read Example REGISTER DESCRIPTIONS REGISTER ARRAY ASSIGNMENTS Enable Bits Image Reject and Band-Pass Filter Bits Band-Pass Filter Bits: OTP and SPI AGC AGC: IF Gain Limit Bits Band-Pass Filter Bits: Calibration and 8-Bit Word Frequency AGC: Blocker Power Detector Bits Phase I Bits Phase Q Bits APPLICATIONS INFORMATION SCHEMATIC/TYPICAL APPLICATION CIRCUIT EVALUATION PRINTED CIRCUIT BOARD (PCB) OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet HMC8100LP6JE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS K_P N P _ _ CL Q Q _ K _ _ F T O I L N P M M RE RS SD SD SC SEN LO LO IR IR 40 39 38 37 36 35 34 33 32 31 DVDD 1 30 VDD AMP2_P 2 29 IRM_I_N AMP2_N 3 28 IRM_I_P VCC_FILTER 4 27 VCC_IRM HMC8100 FILTER2P 5 26 VCC_VGA1_BALUN VCC_AMP3 6 TOP VIEW 25 VCC_VGA1 GND1 7 (Not to Scale) 24 FILTER1P VCC_BB 8 23 VCC_AMP1 GND2 9 22 AMP1 VGA_EXT_CAP 10 21 GND 11 12 13 14 15 16 17 18 19 20 T 3 1 T U A IN UT IN _ D U G SSI O 3 R CAP CAP O _ RF _ _ _ _ PD T F F 1 RX_O _I CC_P CC_V U AUX A _R V PD V O _ G A 3 V G _ V PD C _ V C V
2
NOTES
-00
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A LOW
7
IMPEDANCE THERMAL AND ELECTRICAL GROUND PLANE.
86 13 Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 DVDD SPI Digital Power Supply (3.3 V dc). See Figure 52 for the required components. 2 AMPT2_P Second Differential Amplifier Output (Positive). 3 AMP2_N Second Differential Amplifier Output (Negative). 4 VCC_FILTER Power Supply for the Filter (3.3 V dc). See Figure 52 for the required components. 5 FILTER2P Input of the Third External Filter Amplifier. 6 VCC_AMP3 Power Supply for the Third External Filter Amplifier (3.3 V dc). See Figure 52 for the required components. 7, 9, 21 GND1, GND2, GND3 Ground Connect. 8 VCC_BB Power Supply for the Baseband Blocks (3.3 V dc). See Figure 52 for the required components. 10 VGA_EXT_CAP External Capacitor for VGA3. See Figure 52 for the required components. 11 RX_OUT Receiver Output. 12 VCC_VGA3 Power Supply for VGA3 (3.3 V dc). See Figure 52 for the required components. 13 AUX_OUT Receiver Auxiliary Output. 14 PD3_IN Receive AGC Loop Input. 15 PD3_OUT/RSSI Third Power Detector Output. 16 VC_VGA_IF/CAP− Control Voltage of IFVGA/AGC Integrator Capacitor. See Figure 52 for the required components. 17 VC_VGA_RF/CAP+ Control Voltage of RFVGA/AGC Integrator Capacitor. See Figure 52 for the required components. 18 VCC_PD1 Power Supply for the First Power Detector (3.3 V dc). See Figure 52 for the required components. 19 PD1_OUT First Power Detector Output. 20 RFIN Radio Frequency Input. This pin is matched to 50 Ω. 22 AMP1 Single-Ended Output of Amplifier 1 (3.3 V dc). See Figure 52 for the required components. 23 VCC_AMP1 Power Supply for AMP1 (3.3 V dc). See Figure 52 for the required components. 24 FILTER1P RFVGA Input. 25 VCC_VGA1 Power Supply for the RFVGA (3.3 V dc). See Figure 52 for the required components. 26 VCC_VGA1_BALUN Power Supply for RFVGA Balun(3.3 V dc). See Figure 52 for the required components. 27 VCC_IRM Power Supply for the Image Reject Mixer (3.3 V dc). See Figure 52 for the required components. 28 IRM_I_P Positive In-Phase IF Output for the Image Reject Mixer. 29 IRM_I_N Negative In-Phase IF Output for the Image Reject Mixer. 30 VDD Power Supply for Logic Circuitry (3.3 V dc). See Figure 52 for the required components. 31 IRM_Q_P Positive Quadrature IF Output for the Image Reject Mixer. 32 IRM_Q_N Negative Quadrature IF Output for the Image Reject Mixer. 33 LOP Local Oscillator Input (Positive). This pin is ac-coupled and matched to 50 Ω. Rev. B | Page 7 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS: 800 MHz TO 1800 MHz RF FREQUENCY RANGE ELECTRICAL CHARACTERISTICS: 1800 MHz TO 2800 MHz RF FREQUENCY RANGE ELECTRICAL CHARACTERISTICS: 2800 MHz TO 4000 MHz RF FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL AGC CONFIGURATION INTERNAL AGC CONFIGURATION THEORY OF OPERATION REGISTER ARRAY ASSIGNMENTS AND SERIAL INTERFACE Read Example REGISTER DESCRIPTIONS REGISTER ARRAY ASSIGNMENTS Enable Bits Image Reject and Band-Pass Filter Bits Band-Pass Filter Bits: OTP and SPI AGC AGC: IF Gain Limit Bits Band-Pass Filter Bits: Calibration and 8-Bit Word Frequency AGC: Blocker Power Detector Bits Phase I Bits Phase Q Bits APPLICATIONS INFORMATION SCHEMATIC/TYPICAL APPLICATION CIRCUIT EVALUATION PRINTED CIRCUIT BOARD (PCB) OUTLINE DIMENSIONS ORDERING GUIDE
