Datasheet HMC8100LP6JE (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Intermediate Frequency Receiver, 800 MHz to 4000 MHz |
| Pages / Page | 27 / 8 — HMC8100LP6JE. Data Sheet |
| Revision | B |
| File Format / Size | PDF / 745 Kb |
| Document Language | English |
HMC8100LP6JE. Data Sheet
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HMC8100LP6JE Data Sheet
34 LON Local Oscillator Input (Negative). This pin is ac-coupled and matched to 50 Ω. 35 SEN SPI Serial Enable. 36 SCLK SPI Clock Digital Input. 37 SDI SPI Serial Data Input. 38 SDO SPI Serial Data Output. 39 RST SPI Reset. RESET must be held low (Logic 0) during power on. This is critical for proper programming and reliable operation. Refer to the Theory of Operation section. 40 REF_CLK_P Filter Calibration Clock. EPAD Exposed Pad. Connect the exposed pad to a low impedance thermal and electrical ground plane. Rev. B | Page 8 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS: 800 MHz TO 1800 MHz RF FREQUENCY RANGE ELECTRICAL CHARACTERISTICS: 1800 MHz TO 2800 MHz RF FREQUENCY RANGE ELECTRICAL CHARACTERISTICS: 2800 MHz TO 4000 MHz RF FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL AGC CONFIGURATION INTERNAL AGC CONFIGURATION THEORY OF OPERATION REGISTER ARRAY ASSIGNMENTS AND SERIAL INTERFACE Read Example REGISTER DESCRIPTIONS REGISTER ARRAY ASSIGNMENTS Enable Bits Image Reject and Band-Pass Filter Bits Band-Pass Filter Bits: OTP and SPI AGC AGC: IF Gain Limit Bits Band-Pass Filter Bits: Calibration and 8-Bit Word Frequency AGC: Blocker Power Detector Bits Phase I Bits Phase Q Bits APPLICATIONS INFORMATION SCHEMATIC/TYPICAL APPLICATION CIRCUIT EVALUATION PRINTED CIRCUIT BOARD (PCB) OUTLINE DIMENSIONS ORDERING GUIDE
HMC8100LP6JE Data Sheet
34 LON Local Oscillator Input (Negative). This pin is ac-coupled and matched to 50 Ω. 35 SEN SPI Serial Enable. 36 SCLK SPI Clock Digital Input. 37 SDI SPI Serial Data Input. 38 SDO SPI Serial Data Output. 39 RST SPI Reset. RESET must be held low (Logic 0) during power on. This is critical for proper programming and reliable operation. Refer to the Theory of Operation section. 40 REF_CLK_P Filter Calibration Clock. EPAD Exposed Pad. Connect the exposed pad to a low impedance thermal and electrical ground plane. Rev. B | Page 8 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS: 800 MHz TO 1800 MHz RF FREQUENCY RANGE ELECTRICAL CHARACTERISTICS: 1800 MHz TO 2800 MHz RF FREQUENCY RANGE ELECTRICAL CHARACTERISTICS: 2800 MHz TO 4000 MHz RF FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL AGC CONFIGURATION INTERNAL AGC CONFIGURATION THEORY OF OPERATION REGISTER ARRAY ASSIGNMENTS AND SERIAL INTERFACE Read Example REGISTER DESCRIPTIONS REGISTER ARRAY ASSIGNMENTS Enable Bits Image Reject and Band-Pass Filter Bits Band-Pass Filter Bits: OTP and SPI AGC AGC: IF Gain Limit Bits Band-Pass Filter Bits: Calibration and 8-Bit Word Frequency AGC: Blocker Power Detector Bits Phase I Bits Phase Q Bits APPLICATIONS INFORMATION SCHEMATIC/TYPICAL APPLICATION CIRCUIT EVALUATION PRINTED CIRCUIT BOARD (PCB) OUTLINE DIMENSIONS ORDERING GUIDE
