Datasheet MAX9910, MAX9911, MAX9912, MAX9913 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 200kHz, 4µA, Rail-to-Rail I/O Op Amps with Shutdown |
| Pages / Page | 17 / 10 — 200kHz, 4µA, Rail-to-Rail I/O Op Amps with Shutdown. RAIL-TO-RAIL OUTPUT … |
| File Format / Size | PDF / 515 Kb |
| Document Language | English |
200kHz, 4µA, Rail-to-Rail I/O Op Amps with Shutdown. RAIL-TO-RAIL OUTPUT VOLTAGE RANGE. Power-Up Settling Time. Shutdown Mode
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200kHz, 4µA, Rail-to-Rail I/O Op Amps with Shutdown
rejection ratio of 95dB (typ) allows the devices to be powered directly from a battery, simplifying design and
RAIL-TO-RAIL OUTPUT VOLTAGE RANGE
extending battery life. 3V
Power-Up Settling Time
IN_ The MAX9910–MAX9913 typically require 5µs after power-up. Supply settling time depends on the supply 1V/div voltage, the value of the bypass capacitor, the output impedance of the incoming supply, and any lead resis- 0V tance or inductance between components. Op-amp 3V settling time depends primarily on the output voltage OUT_ and is slew-rate limited. Figure 3 shows the MAX991_ in a noninverting voltage follower configuration with the 1V/div input held at midsupply. The output settles in approxi- mately 18µs for V 0V DD = 3V (see the Typical Operating Characteristics for power-up settling time). 200µs/div
Shutdown Mode
Figure 1. Rail-to-Rail Output Voltage Range The MAX9911/MAX9913 feature active-low shutdown
MAX9910–MAX9913
inputs. The MAX9911/MAX9913 enter shutdown in 2µs (typ) and exit in 30µs (typ). The amplifiers’ outputs are in a high-impedance state in shutdown mode. Drive SHDN low to enter shutdown. Drive SHDN high to enable the amplifier. The MAX9913 dual-amplifier fea- RISO tures separate shutdown inputs. Shut down both ampli- MAX9910– fiers for the lowest quiescent current. MAX9913 RL CL
Power-Supply Bypassing and Layout
To minimize noise, bypass VDD with a 0.1µF capacitor to ground, as close to the pin as possible. Good layout techniques optimize performance RL AV = ≈ 1V/V by decreasing the amount of stray capacitance and RL + RISO inductance to the op amps’ inputs and outputs. Minimize stray capacitance and inductance by placing Figure 2. Using a Resistor to Isolate a Capacitive Load from external components close to the IC. the Op Amp 5.5V 0V IN- VDD 100kΩ OUT MAX991_ IN+ VSS 100kΩ Figure 3. Power-Up Test Configuration
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rejection ratio of 95dB (typ) allows the devices to be powered directly from a battery, simplifying design and
RAIL-TO-RAIL OUTPUT VOLTAGE RANGE
extending battery life. 3V
Power-Up Settling Time
IN_ The MAX9910–MAX9913 typically require 5µs after power-up. Supply settling time depends on the supply 1V/div voltage, the value of the bypass capacitor, the output impedance of the incoming supply, and any lead resis- 0V tance or inductance between components. Op-amp 3V settling time depends primarily on the output voltage OUT_ and is slew-rate limited. Figure 3 shows the MAX991_ in a noninverting voltage follower configuration with the 1V/div input held at midsupply. The output settles in approxi- mately 18µs for V 0V DD = 3V (see the Typical Operating Characteristics for power-up settling time). 200µs/div
Shutdown Mode
Figure 1. Rail-to-Rail Output Voltage Range The MAX9911/MAX9913 feature active-low shutdown
MAX9910–MAX9913
inputs. The MAX9911/MAX9913 enter shutdown in 2µs (typ) and exit in 30µs (typ). The amplifiers’ outputs are in a high-impedance state in shutdown mode. Drive SHDN low to enter shutdown. Drive SHDN high to enable the amplifier. The MAX9913 dual-amplifier fea- RISO tures separate shutdown inputs. Shut down both ampli- MAX9910– fiers for the lowest quiescent current. MAX9913 RL CL
Power-Supply Bypassing and Layout
To minimize noise, bypass VDD with a 0.1µF capacitor to ground, as close to the pin as possible. Good layout techniques optimize performance RL AV = ≈ 1V/V by decreasing the amount of stray capacitance and RL + RISO inductance to the op amps’ inputs and outputs. Minimize stray capacitance and inductance by placing Figure 2. Using a Resistor to Isolate a Capacitive Load from external components close to the IC. the Op Amp 5.5V 0V IN- VDD 100kΩ OUT MAX991_ IN+ VSS 100kΩ Figure 3. Power-Up Test Configuration
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